The PCM5252 is a monolithic CMOS integrated circuit that includes a
stereo digital-to-analog converter and additional support circuitry in a small QFN package. The
PCM5252 uses the latest generation of TI’s advanced segment-DAC architecture
to achieve excellent dynamic performance and improved tolerance to clock jitter.
The PCM5252 integrates a fully programmable miniDSP core, allowing
developers to integrate filters, dynamic range controls, custom interpolators and other
differentiating features to their products.
The PCM5252 integrates ROM components of TI’s
PurePath™ Smart Amp technology, which allows speakers to be driven with more peak power than their
average-power rating, without damage to the speaker by voice coil over excursion or thermal
overload.
The PCM5252 provides 4.2VRMS ground-centered
differential outputs, allowing designers to eliminate DC blocking capacitors on the output, as well
as external muting circuits traditionally associated with single supply line drivers.
The integrated PLL on the device removes the requirement for a system clock (commonly
known as master clock), allowing a 3-wire I2S connection and reducing
system EMI.
Block diagrams for the can be found at Functional Block Diagram.
The PCM5252 is a monolithic CMOS integrated circuit that includes a
stereo digital-to-analog converter and additional support circuitry in a small QFN package. The
PCM5252 uses the latest generation of TI’s advanced segment-DAC architecture
to achieve excellent dynamic performance and improved tolerance to clock jitter.
The PCM5252 integrates a fully programmable miniDSP core, allowing
developers to integrate filters, dynamic range controls, custom interpolators and other
differentiating features to their products.
The PCM5252 integrates ROM components of TI’s
PurePath™ Smart Amp technology, which allows speakers to be driven with more peak power than their
average-power rating, without damage to the speaker by voice coil over excursion or thermal
overload.
The PCM5252 provides 4.2VRMS ground-centered
differential outputs, allowing designers to eliminate DC blocking capacitors on the output, as well
as external muting circuits traditionally associated with single supply line drivers.
The integrated PLL on the device removes the requirement for a system clock (commonly
known as master clock), allowing a 3-wire I2S connection and reducing
system EMI.
Block diagrams for the can be found at Functional Block Diagram.