Home Amplifiers Programmable & variable gain amplifiers (PGAs & VGAs)
Home
Amplifiers
Programmable & variable gain amplifiers (PGAs & VGAs)

PGA116

ACTIVE

Zero-Drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp w

Order now
Data sheet

PGA116

ACTIVE
Data sheet Order now

Product details

Features Binary gains, Daisy chain, Shutdown PGA/VGA PGA Number of channels 10 Interface type SPI Vs (max) (V) 5.5 Vs (min) (V) 2.2 Input type Single-ended Vos (offset voltage at 25°C) (typ) (V) 0.000025 Input offset drift (±) (typ) (V/°C) 0.0000006 Input voltage noise (typ) (V√Hz) 0.000000012 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain (max) (dB) 42 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Architecture CMOS Operating temperature range (°C) -40 to 125 Noise at 1 kHz (typ) (V√Hz) 0.000000013 Output type Single-ended
Features Binary gains, Daisy chain, Shutdown PGA/VGA PGA Number of channels 10 Interface type SPI Vs (max) (V) 5.5 Vs (min) (V) 2.2 Input type Single-ended Vos (offset voltage at 25°C) (typ) (V) 0.000025 Input offset drift (±) (typ) (V/°C) 0.0000006 Input voltage noise (typ) (V√Hz) 0.000000012 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain (max) (dB) 42 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Architecture CMOS Operating temperature range (°C) -40 to 125 Noise at 1 kHz (typ) (V√Hz) 0.000000013 Output type Single-ended
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
filter Find other Programmable & variable gain amplifiers (PGAs & VGAs)
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device
PGA117 ACTIVE Zero-drift, 100-µV offset, 12-nV/√Hz noise, RRO (scope gain) programmable gain amp with 10-ch mux This device offers scope gains 1, 2, 5, 10, 20, 50, 100, 200 instead of binary gains
Same functionality with different pin-out to the compared device
PGA112 ACTIVE Zero-drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp with 2-ch mux This device offers 2 channel mux instead of 10 channel mux.
PGA113 ACTIVE Zero-drift, 100-µV offset, 12-nV/√Hz noise, RRO (scope gain) programmable gain amp with 2-ch mux This device offers 2 channel mux instead of 10 channel mux, and scope gains instead of binary gains.

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet PGA11x Zerø-Drift Programmable Gain Amplifier With Mux datasheet (Rev. C) PDF | HTML 30 Nov 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
View Options
Reference designs

TIDA-00191 — Analog Front End for Motor Electronic Overload Relays with Enhanced Current Range

This reference design is the analog front end (AFE) for an electronic overload relay, used for monitoring and protecting motors from overcurrent or undercurrent events. It is an ideal tool for developers creating overload relays for sensitive AC motors in industrial applications. This programmable (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos