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SN54SC8T541-SEP

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Radiation-tolerant 8-bit fixed-direction level translator with 3-state outputs

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Data sheet

SN54SC8T541-SEP

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Data sheet Order now

Product details

Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Rating Space Operating temperature range (°C) -40 to 125
Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Rating Space Operating temperature range (°C) -40 to 125
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • VID TBD
  • Radiation Tolerant:
    • Single Event Latch-Up (SEL) immune up to 43MeV-cm2/mg at 125°C
    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)
    • Single Event Transient (SET) characterized up to LET = 43MeV-cm2/mg

  • Wide operating range of 1.2V to 5.5V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2V to 1.8V

      • 1.5V to 2.5V

      • 1.8V to 3.3V

      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mAper JESD 17
  • Space enhanced plastic:
    • Controlled baseline
    • Au bondwire and NiPdAu lead finish
    • Meets NASA ASTM E595 outgassing specification
    • One fabrication, assembly, and test site
    • Extended product life cycle
    • Product traceability
  • VID TBD
  • Radiation Tolerant:
    • Single Event Latch-Up (SEL) immune up to 43MeV-cm2/mg at 125°C
    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)
    • Single Event Transient (SET) characterized up to LET = 43MeV-cm2/mg

  • Wide operating range of 1.2V to 5.5V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2V to 1.8V

      • 1.5V to 2.5V

      • 1.8V to 3.3V

      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mAper JESD 17
  • Space enhanced plastic:
    • Controlled baseline
    • Au bondwire and NiPdAu lead finish
    • Meets NASA ASTM E595 outgassing specification
    • One fabrication, assembly, and test site
    • Extended product life cycle
    • Product traceability

The SN54SC8T541-SEP contains eight buffers with 3-state outputs. The active low output enable pins (OE1 and OE2) control all eight channels, and are configured so that both must be low for the outputs to be active. When the outputs are enabled, the outputs are actively driven low or high. When the outputs are disabled, the outputs are set into the high-impedance state. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN54SC8T541-SEP contains eight buffers with 3-state outputs. The active low output enable pins (OE1 and OE2) control all eight channels, and are configured so that both must be low for the outputs to be active. When the outputs are enabled, the outputs are actively driven low or high. When the outputs are disabled, the outputs are set into the high-impedance state. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
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* Data sheet SN54SC8T541-SEP Radiation Tolerant, Octal Buffers and Line Drivers With 3-State Outputs and Logic Level Shifter datasheet PDF | HTML 19 Apr 2024

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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TSSOP (PW) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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