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SN65LVDS4

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500-Mbps LVDS single high-speed receiver

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Data sheet

SN65LVDS4

ACTIVE
Data sheet Order now

Product details

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 1 Supply voltage (V) 1.8, 2.5 Signaling rate (Mbps) 500 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 1 Supply voltage (V) 1.8, 2.5 Signaling rate (Mbps) 500 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
UQFN (RSE) 10 3 mm² 2 x 1.5
  • Designed for Signaling Rates(1) up to:
    • 500-Mbps Receiver
  • Operates From a 1.8-V or 2.5-V Core Supply
  • Available in 1.5-mm × 2-mm UQFN Package
  • Bus-Terminal ESD Exceeds 2 kV (HBM)
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 350 mV Into a 100-Ω Load
  • Propagation Delay Times
    • 2.1 ns Typical Receiver
  • Power Dissipation at 250 MHz
    • 40 mW Typical
  • Requires External Failsafe
  • Differential Input Voltage Threshold Less Than 50
    mV
  • Can Provide Output Voltage Logic Level (3.3-V
    LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
    on External VDD Pin, Thus Eliminating External
    LevelTranslation
  • Designed for Signaling Rates(1) up to:
    • 500-Mbps Receiver
  • Operates From a 1.8-V or 2.5-V Core Supply
  • Available in 1.5-mm × 2-mm UQFN Package
  • Bus-Terminal ESD Exceeds 2 kV (HBM)
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 350 mV Into a 100-Ω Load
  • Propagation Delay Times
    • 2.1 ns Typical Receiver
  • Power Dissipation at 250 MHz
    • 40 mW Typical
  • Requires External Failsafe
  • Differential Input Voltage Threshold Less Than 50
    mV
  • Can Provide Output Voltage Logic Level (3.3-V
    LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
    on External VDD Pin, Thus Eliminating External
    LevelTranslation

The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.

The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.
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Technical documentation

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Type Title Date
* Data sheet SN65LVDS4 1.8-V High-Speed Differential Line Receiver datasheet (Rev. A) PDF | HTML 30 Nov 2015
Application brief How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver 09 Jan 2019
Application brief How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter 28 Dec 2018
Application brief LVDS to Improve EMC in Motor Drives 27 Sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 Aug 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 May 2018
Application note TMDS Clock Detection Solution in HDMI Sink Applications 23 Aug 2017
Technical article Get Connected: High-speed LVDS comparator PDF | HTML 03 Jun 2015
EVM User's guide SN65LVDS4 Evaluation Module 15 Jul 2011

Design & development

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SN65LVDS4EVM — SN65LVDS4 Evaluation Module

Evaluation Module for SN65LVDS4
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SN65LVDS4 IBIS Model

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-01378 — Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications

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TIDA-00732 — 18-bit, 2-Msps Isolated Data Acquisition Reference Design to Achieve Maximum SNR and Sampling Rate

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Schematic: PDF
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Design guide: PDF
Schematic: PDF
Reference designs

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UQFN (RSE) 10 Ultra Librarian
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