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SN74AHCT367

ACTIVE

6-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs

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Data sheet

SN74AHCT367

ACTIVE
Data sheet Order now

Product details

Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 6 IOL (max) (mA) 8 Supply current (max) (µA) 40 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 6 IOL (max) (mA) 8 Supply current (max) (µA) 40 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 16 59.4 mm² 9.9 x 6 SSOP (DB) 16 48.36 mm² 6.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4
  • Inputs are TTL-voltage compatible
  • True outputs
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000V human-body model
    • 2000V charged-device model
  • Inputs are TTL-voltage compatible
  • True outputs
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000V human-body model
    • 2000V charged-device model

The SN74AHCT367 device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74AHCT367 device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

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SN74AHC367 ACTIVE 6-ch, 2-V to 5.5-V buffers with 3-state outputs Voltage range (2V to 5.5V), average drive strength (9mA), average propagation delay (12ns)

Technical documentation

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Type Title Date
* Data sheet SN74AHCT367 Hex Buffer and Line Driver with 3-State Output datasheet (Rev. I) PDF | HTML 22 Jul 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74AHCT367 Behavioral SPICE Model

SCLM240.ZIP (7 KB) - PSpice Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 16 Ultra Librarian
SSOP (DB) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
TVSOP (DGV) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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