These 8-bit D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted outputs.
A buffered output-enable (
) input places the eight outputs in either a normal
logic state (high or low logic levels) or a high-impedance state. In
the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive
provide the capability to drive bus lines without interface or pullup
components.
does not affect
the internal operations of the latches. Old data can be retained or
new data can be entered while the outputs are off.
The SN74ALS533A and SN74AS533A are characterized for operation from 0°C to 70°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Octal D-Type Transparent Latches With 3-State Outputs datasheet | 01 Dec 1994 |
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