This 9-bit bus-interface D-type latch features 3-state outputs
designed specifically for driving
highly capacitive or relatively low-impedance loads. It is
particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The nine latches are transparent D-type latches with noninverting
data (D) inputs.
A buffered output-enable () input places the nine outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive
provide the capability to drive bus lines without interface or pullup
components.
does not
affect the internal operation of the latches. Previously stored data
can be retained or new data can be entered while the outputs are off.
The SN74ALS843 is characterized for operation from 0°C to
70°C.
This 9-bit bus-interface D-type latch features 3-state outputs
designed specifically for driving
highly capacitive or relatively low-impedance loads. It is
particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The nine latches are transparent D-type latches with noninverting
data (D) inputs.
A buffered output-enable () input places the nine outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive
provide the capability to drive bus lines without interface or pullup
components.
does not
affect the internal operation of the latches. Previously stored data
can be retained or new data can be entered while the outputs are off.
The SN74ALS843 is characterized for operation from 0°C to
70°C.