SN74ALVCH244

Name: SN74ALVCH244
Brand: TI
SKU: SN74ALVCH244
Price: 0.204 USD

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8-ch, 1.65-V to 3.6-V buffers with bus-hold and 3-state outputs

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Data sheet

document-pdfAcrobat SN74ALVCH244 datasheet (Rev. F)

SN74ALVCH244

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Data sheet

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Product details

Technology family

ALVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

8

IOL (max) (mA)

24

Supply current (max) (µA)

10

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ALVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

8

IOL (max) (mA)

24

Supply current (max) (µA)

10

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

TVSOP (DGV)

20

32 mm² 5 x 6.4

Operates From 1.65 V to 3.6 V
Max t_pd of 2.8 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Operates From 1.65 V to 3.6 V
Max t_pd of 2.8 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

This octal buffer/line driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This octal buffer/line driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74ALVCH244 datasheet (Rev. F)	20 Aug 2004
	Application note	An Overview of Bus-Hold Circuit and the Applications (Rev. B)	17 Sep 2018
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dec 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	User guide	ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)	01 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 May 2002
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)	08 Sep 1999
	Application note	TI SN74ALVC16835 Component Specification Analysis for PC100	03 Aug 1998
	Application note	Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)	13 May 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dec 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Oct 1996
	Application note	Live Insertion	01 Oct 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 May 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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