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SN74AUC1GU04

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Single 0.8-V to 2.7-V high speed inverter

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Data sheet

SN74AUC1GU04

ACTIVE
Data sheet Order now

Product details

Technology family AUC Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 2.7 Number of channels 1 IOL (max) (mA) 9 IOH (max) (mA) -9 Supply current (max) (µA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns), Unbuffered Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUC Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 2.7 Number of channels 1 IOL (max) (mA) 9 IOH (max) (mA) -9 Supply current (max) (µA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns), Unbuffered Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Sub-1-V Operable
  • Max tpd of 2.4 ns at 1.8 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Unbuffered Output
  • Ioff Supports Partial Power Down Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Sub-1-V Operable
  • Max tpd of 2.4 ns at 1.8 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Unbuffered Output
  • Ioff Supports Partial Power Down Mode and Back Drive Protection

This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1GU04 device contains one inverter with an unbuffered output and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1GU04 device contains one inverter with an unbuffered output and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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Technical documentation

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Type Title Date
* Data sheet SN74AUC1GU04 Single Inverter Gate datasheet (Rev. M) PDF | HTML 08 Jun 2017
Application brief Generate a Clock Signal from a Crystal Oscillator PDF | HTML 08 Oct 2020
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
Application note Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices 21 Mar 2003
User guide AUC Data Book, January 2003 (Rev. A) 01 Jan 2003
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
More literature AUC Product Brochure (Rev. A) 18 Mar 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

HSPICE Model of SN74AUC1GU04

SCEJ135.ZIP (40 KB) - HSpice Model
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Simulation model

SN74AUC1GU04 Behavioral SPICE Model

SCEM718.ZIP (7 KB) - PSpice Model
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Simulation model

SN74AUC1GU04 IBIS Model (Rev. B)

SCEM225B.ZIP (56 KB) - IBIS Model
Download
Package Pins CAD symbols, footprints & 3D models
DSBGA (YZP) 5 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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