SN74HC273-Q1

Name: SN74HC273-Q1
Brand: TI
SKU: SN74HC273-Q1
Price: 0.341 USD

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Automotive Catalog Octal D-Type Flip-Flops With Clear

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Data sheet

document-pdfAcrobat Octal D-Type Flip-Flop With Clear datasheet (Rev. A)

SN74HC273-Q1

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Data sheet

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Product details

Number of channels

8

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

28

IOL (max) (mA)

5.2

IOH (max) (mA)

-5.2

Supply current (max) (µA)

80

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Number of channels

8

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

28

IOL (max) (mA)

5.2

IOH (max) (mA)

-5.2

Supply current (max) (µA)

80

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

Qualified for Automotive Applications
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 160-µA Max I_CC
Typical t_pd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Contain Eight Flip-Flops With Single-Rail Outputs
Direct Clear Input
Individual Data Input to Each Flip-Flop
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators

Qualified for Automotive Applications
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 160-µA Max I_CC
Typical t_pd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Contain Eight Flip-Flops With Single-Rail Outputs
Direct Clear Input
Individual Data Input to Each Flip-Flop
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators

This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

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