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SN74LV166A

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8-Bit Parallel-Load Shift Registers

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Data sheet

SN74LV166A

ACTIVE
Data sheet Order now

Product details

Configuration Parallel-in, Serial-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 45 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Configuration Parallel-in, Serial-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 45 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 SSOP (DB) 16 48.36 mm² 6.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4
  • Operation of 2 V to 5.5 V VCC
  • Max tpd of 10.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) 2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports partial-power-down-mode operation
  • Synchronous load
  • Direct overriding clear
  • Parallel-to-serial conversion
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • Operation of 2 V to 5.5 V VCC
  • Max tpd of 10.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) 2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports partial-power-down-mode operation
  • Synchronous load
  • Direct overriding clear
  • Parallel-to-serial conversion
  • Latch-up performance exceeds 100 mA per JESD 78, Class II

The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2 V to 5.5 V VCC operation.

The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2 V to 5.5 V VCC operation.
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Technical documentation

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* Data sheet SN74LV166A 8-Bit Parallel-Load Shift Registers datasheet (Rev. D) PDF | HTML 16 Mar 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
SSOP (DB) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
TVSOP (DGV) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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