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Noninverting buffers & drivers

SN74LVC07A

ACTIVE

6-ch, 1.65-V to 5.5-V buffers with open-drain outputs

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Data sheet

SN74LVC07A

ACTIVE
Data sheet Order now

Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 6 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 6 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Operates From 1.65 V to 5 V
  • Inputs and Open-Drain Outputs Accept Voltages Up to 5.5 V
  • Max tpd of 2.6 ns at 5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Operates From 1.65 V to 5 V
  • Inputs and Open-Drain Outputs Accept Voltages Up to 5.5 V
  • Max tpd of 2.6 ns at 5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection

The SN74LVC07A device is a hex buffer and driver that is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC07A device is a hex buffer and driver that is designed for 1.65-V to 5.5-V VCC operation.
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Technical documentation

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Type Title Date
* Data sheet SN74LVC07A Hex Buffer and Driver With Open-Drain Outputs datasheet (Rev. W) PDF | HTML 13 Nov 2015
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note LVC07A: Applications Of An Open-Drain Hex Buffer And Discussion Of Char Results 08 Apr 1999
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LVC07A Behavioral SPICE Model

SCAM113.ZIP (7 KB) - PSpice Model
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Simulation model

SN74LVC07A IBIS Model (Rev. C)

SCEM164C.ZIP (27 KB) - IBIS Model
Download
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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