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CD4047B

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CMOS 低功耗单稳态/不稳定多谐振荡器

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CD4047B

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米6体育平台手机版_好二三四详情

Number of channels 1 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Technology family CD4000 Input type Standard CMOS Output type Push-Pull Supply current (µA) 600 IOL (max) (mA) 4 IOH (max) (mA) -4 Features Balanced outputs, Positive input clamp diode, Retriggerable, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 1 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Technology family CD4000 Input type Standard CMOS Output type Push-Pull Supply current (µA) 600 IOL (max) (mA) 4 IOH (max) (mA) -4 Features Balanced outputs, Positive input clamp diode, Retriggerable, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Lower power consumption: special CMOS oscillator configuration
  • Monostable (one-shot) or astable (free-running) operation
  • True and complemented buffered outputs
  • Only one external R anc C required
  • Buffered inputs
  • 100% tested for quiescent current at 20 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Monostable Multivibrator Features:
    • Positive-or negative-edge trigger
    • Output pulse width independent of trigger pulse duration
    • Retriggerable option for pulse width expansion
    • Internal power-on reset circuit
    • Long pulse widths possible using small RC components by means of external counter provision
    • Fast recovery time essentially independent of pulse width
    • Pulse-width accuracy maintained at duty cycles approaching 100%
  • Astable Multivibrator Features:
    • Free-running or gatable operating modes
    • 50% duty cycle
    • Oscillator output available
    • Good astable frequency stability:
         Frequency deviation:
           = ±2% + 0.03%/°C @ 100 kHz
           = ±0.5% +0.015%/°C @ 10 kHz (circuits "trimmed" to frequency VDD = 10 V ± 10%)
  • Applications:
    Digital equipment where low-power dissipation and/or high noise immunity are primary design requirements:
    • Envelope detection
    • Frequency multiplication
    • Frequency division
    • Frequency discriminators
    • Timing circuits
    • Time-delay applications

Data sheet acquired from Harris Semiconductor
  • Lower power consumption: special CMOS oscillator configuration
  • Monostable (one-shot) or astable (free-running) operation
  • True and complemented buffered outputs
  • Only one external R anc C required
  • Buffered inputs
  • 100% tested for quiescent current at 20 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Monostable Multivibrator Features:
    • Positive-or negative-edge trigger
    • Output pulse width independent of trigger pulse duration
    • Retriggerable option for pulse width expansion
    • Internal power-on reset circuit
    • Long pulse widths possible using small RC components by means of external counter provision
    • Fast recovery time essentially independent of pulse width
    • Pulse-width accuracy maintained at duty cycles approaching 100%
  • Astable Multivibrator Features:
    • Free-running or gatable operating modes
    • 50% duty cycle
    • Oscillator output available
    • Good astable frequency stability:
         Frequency deviation:
           = ±2% + 0.03%/°C @ 100 kHz
           = ±0.5% +0.015%/°C @ 10 kHz (circuits "trimmed" to frequency VDD = 10 V ± 10%)
  • Applications:
    Digital equipment where low-power dissipation and/or high noise immunity are primary design requirements:
    • Envelope detection
    • Frequency multiplication
    • Frequency division
    • Frequency discriminators
    • Timing circuits
    • Time-delay applications

Data sheet acquired from Harris Semiconductor

CD4047B consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options.

Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE\, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q\, Q and OSCILLATOR. In all modes of operation, and external capacitor must be connected between C-Timing and RC-Common terminal, and an external resistor must be connected between the R-Timing and RC-Common terminals.

Astable operation is enabled by a high level on the STABLE input or a low level on the ASTABLE\ input, or both. The period of the square wave at the Q and Q\ Outputs in this mode off operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE\ input allow the circuit to be used as a gatable multivibrator. The OSCILLATOR output period will be half of the Q terminal output in the astable mode. However, a 50% duty cycle is not guaranteed at this output.

The CD4047B triggers in the monostable mode when a positive-going edge occurs on the +TRIGGER-input while the -TRIGGER is held low. INput pulses may be of any duration relative to the output pulse.

If retrigger capability is desired, the RETRIGGER input is pulsed. The retriggerable mode of operation is limited to positive-going edge. The CD4047B will retrigger as long as the RETRIGGER-input is high, with or without transitions (See Fig. 34).

An external countdown option can be implemented by coupling "Q" to an external "N" counter and resetting the counter with the trigger pulse. The counter output pulse is fed back to the ASTABLE\ input and has a duration equal to N times the period of the multivibrator.

A high level on the EXTERNAL RESET input assures no output pulse during an "ON" power condition. This input can also be activated to terminate the output pulse at any tine. For monostable operation, whenever VDD is applied, and internal power-on reset circuit will clock the Q output low within one output period (tM).

The CD4047B-Series types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4047B consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options.

Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE\, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q\, Q and OSCILLATOR. In all modes of operation, and external capacitor must be connected between C-Timing and RC-Common terminal, and an external resistor must be connected between the R-Timing and RC-Common terminals.

Astable operation is enabled by a high level on the STABLE input or a low level on the ASTABLE\ input, or both. The period of the square wave at the Q and Q\ Outputs in this mode off operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE\ input allow the circuit to be used as a gatable multivibrator. The OSCILLATOR output period will be half of the Q terminal output in the astable mode. However, a 50% duty cycle is not guaranteed at this output.

The CD4047B triggers in the monostable mode when a positive-going edge occurs on the +TRIGGER-input while the -TRIGGER is held low. INput pulses may be of any duration relative to the output pulse.

If retrigger capability is desired, the RETRIGGER input is pulsed. The retriggerable mode of operation is limited to positive-going edge. The CD4047B will retrigger as long as the RETRIGGER-input is high, with or without transitions (See Fig. 34).

An external countdown option can be implemented by coupling "Q" to an external "N" counter and resetting the counter with the trigger pulse. The counter output pulse is fed back to the ASTABLE\ input and has a duration equal to N times the period of the multivibrator.

A high level on the EXTERNAL RESET input assures no output pulse during an "ON" power condition. This input can also be activated to terminate the output pulse at any tine. For monostable operation, whenever VDD is applied, and internal power-on reset circuit will clock the Q output low within one output period (tM).

The CD4047B-Series types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
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类型 标题 下载最新的英语版本 日期
* 数据表 CD4047B TYPES 数据表 (Rev. C) 2003年 8月 21日
应用手册 使用 SN74LVC1G123 单稳多谐振荡器进行设计 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2021年 7月 20日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
应用手册 Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑米6体育平台手机版_好二三四通用评估模块

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用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
TI.com 上无现货
封装 引脚 CAD 符号、封装和 3D 模型
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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