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SN54LS323

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8 位通用移位/存储寄存器

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SN54LS323

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米6体育平台手机版_好二三四详情

Configuration Universal Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 21000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 21000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Multiplexed Inputs/Outputs Provide Improved Bit Density
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Left
    • Shift Right
    • Load Data
  • Operates with Outputs Enabled or at High Z
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Typical Power Dissipation … 175 mW
  • Exceptionally Stable Shift (Clock) Frequency … 25 MHz
  • Applications:
    • Stacked or Push-Down Registers,
    • Buffer Storage, and
    • Accumulator Registers
  • SN54LS299 and SN74LS299 Are Similar But Have Direct Overriding Clear

 
  • Multiplexed Inputs/Outputs Provide Improved Bit Density
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Left
    • Shift Right
    • Load Data
  • Operates with Outputs Enabled or at High Z
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Typical Power Dissipation … 175 mW
  • Exceptionally Stable Shift (Clock) Frequency … 25 MHz
  • Applications:
    • Stacked or Push-Down Registers,
    • Buffer Storage, and
    • Accumulator Registers
  • SN54LS299 and SN74LS299 Are Similar But Have Direct Overriding Clear

 

These Low-Power Schottky eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock.

 

These Low-Power Schottky eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock.

 
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类型 标题 下载最新的英语版本 日期
* 数据表 8-Bit Universal Shift/Storage Registers 数据表 1988年 3月 1日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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