SN65MLVD207
- Low-Voltage Differential 30- Line Drivers and Receivers for Signaling Rates(1) Up to 200 Mbps
- Type-1 Receivers Incorporate 25 mV of Hysteresis
- Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions
- Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
- Controlled Driver Output Voltage Transition Times for Improved Signal Quality
- –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
- Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
- 100-Mbps Devices Available (SN65MLVD200A, 202A, 204A, 205A)
- M-LVDS Bus Power Up/Down Glitch Free
- APPLICATIONS
- Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485 - Backplane or Cabled Multipoint Data and Clock Transmission
- Cellular Base Stations
- Central-Office Switches
- Network Switches and Routers
- Low-Power High-Speed Short-Reach
(1) The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
The SN65MLVD201, 203, 206, and 207 are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 200 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 , and incorporates controlled transition times to allow for stubs off of the backbone transmission line.
These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other faults conditions. The devices are characterized for operation from –40°C to 85°C.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | Multipoint-LVDS Line Driver and Receiver 数据表 (Rev. C) | 2008年 1月 7日 | |||
应用简报 | How Far, How Fast Can You Operate MLVDS? | 2018年 8月 6日 | ||||
应用手册 | Introduction to M-LVDS (TIA/EIA-899) (Rev. A) | 2013年 1月 3日 | ||||
用户指南 | Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. B) | 2004年 4月 5日 | ||||
应用手册 | M-LVDS Signaling Rate Versus Distance | 2003年 4月 9日 | ||||
应用手册 | Interoperability of M-LVDS and BusLVDS | 2003年 2月 6日 | ||||
用户指南 | 200 Mbps Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. A) | 2002年 12月 20日 | ||||
应用手册 | Wired-Logic Signaling with M-LVDS | 2002年 10月 31日 | ||||
应用手册 | TIA/EIA-485 and M-LVDS, Power and Speed Comparison | 2002年 2月 20日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
MLVD20XBEVM — SN65MLVD203B and SN65MLVD204B full-duplex and half-duplex multipoint LVDS (M-LVDS) evaluation module
MLVD20XEVM — M-LVDS 评估模块
SN65MLVD203B 是全双工收发器,SN65MLVD204B 是半双工收发器。
PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®
借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短米6体育平台手机版_好二三四上市时间并降低开发成本。
在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
TINA-TI — 基于 SPICE 的模拟仿真程序
TINA-TI 安装需要大约 500MB。直接安装,如果想卸载也很容易。我们相信您肯定会爱不释手。
TINA 是米6体育平台手机版_好二三四 (TI) 专有的 DesignSoft 米6体育平台手机版_好二三四。该免费版本具有完整的功能,但不支持完整版 TINA 所提供的某些其他功能。
如需获取可用 TINA-TI 模型的完整列表,请参阅:SpiceRack - 完整列表
需要 HSpice (...)
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
SOIC (D) | 14 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
推荐米6体育平台手机版_好二三四可能包含与 TI 此米6体育平台手机版_好二三四相关的参数、评估模块或参考设计。