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SN74FB1653

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具有缓冲时钟线路的 17 位 LVTTL/BTL 通用存储收发器

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数据表

SN74FB1653

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数据表 立即订购

米6体育平台手机版_好二三四详情

Technology family FB Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
Technology family FB Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
HLQFP (PCA) 100 256 mm² 16 x 16
  • Compatible With IEEE Std 1194.1-1991 (BTL)
  • LVTTL A Port, Backplane Transceiver Logic (BTL) B\ Port
  • Open-Collector B\-Port Outputs Sink 100 mA
  • B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
  • High-Impedance State During Power Up and Power Down
  • Selectable Clock Delay
  • TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
  • BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal
  • Compatible With IEEE Std 1194.1-1991 (BTL)
  • LVTTL A Port, Backplane Transceiver Logic (BTL) B\ Port
  • Open-Collector B\-Port Outputs Sink 100 mA
  • B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
  • High-Impedance State During Power Up and Power Down
  • Selectable Clock Delay
  • TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
  • BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal

The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL).

The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.

The B\ port operates at BTL signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB)\ are provided for the B\ outputs. When OEB is low, OEB\ is high, or VCC(5 V) typically is less than 2.5 V, the B port is turned off.

The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer to the MUX-MODE DELAY table).

BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.

BG VCC and BG GND are the supply inputs for the bias generator.

VREF is an internally generated voltage source. It is recommended that VREF be decoupled with a 0.1-µF capacitor.

Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies greater than 50 MHz, or from AI to B\ or B\ to A0 at frequencies greater than 100 MHz.

The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL).

The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.

The B\ port operates at BTL signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB)\ are provided for the B\ outputs. When OEB is low, OEB\ is high, or VCC(5 V) typically is less than 2.5 V, the B port is turned off.

The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer to the MUX-MODE DELAY table).

BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.

BG VCC and BG GND are the supply inputs for the bias generator.

VREF is an internally generated voltage source. It is recommended that VREF be decoupled with a 0.1-µF capacitor.

Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies greater than 50 MHz, or from AI to B\ or B\ to A0 at frequencies greater than 100 MHz.
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类型 标题 下载最新的英语版本 日期
* 数据表 SN74FB1653 数据表 (Rev. H) 2004年 3月 10日
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选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
选择指南 《高级总线接口逻辑器件选择指南》 英语版 2010年 7月 7日
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设计和开发

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仿真模型

SN74FB1653 IBIS Model (Rev. C)

SCBM012C.ZIP (26 KB) - IBIS Model
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封装 引脚 CAD 符号、封装和 3D 模型
HLQFP (PCA) 100 Ultra Librarian
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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