SN74LV245AT

Name: SN74LV245AT
Brand: TI
SKU: SN74LV245AT
Price: 0.164 USD

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数据表

document-pdfAcrobat SN74LV245AT 数据表 (Rev. D) (英语)

SN74LV245AT

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数据表

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Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

16

IOH (max) (mA)

-16

Input type

TTL

Output type

CMOS

Features

Balanced outputs

Technology family

LV-AT

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

16

IOH (max) (mA)

-16

Input type

TTL

Output type

CMOS

Features

Balanced outputs

Technology family

LV-AT

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

TVSOP (DGV)

20

32 mm² 5 x 6.4

VQFN (RGY)

20

15.75 mm² 4.5 x 3.5

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd of 3.5 ns at 5 V
Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2.3 V
at V_CC = 5 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd of 3.5 ns at 5 V
Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2.3 V
at V_CC = 5 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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