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SN74LV393A-EP

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双通道 4 位二进制计数器（增强型米6体育平台手机版_好二三四）

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SN74LV393A-EP

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米6体育平台手机版_好二三四详情

Function Counter Bits (#) 4 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 105 Rating HiRel Enhanced Product
Function Counter Bits (#) 4 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 105 Rating HiRel Enhanced Product
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 105°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 14.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Dual 4-Bit Binary Counters With Individual Clocks
  • Direct Clear for Each 4-Bit Counter
  • Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 105°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 14.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Dual 4-Bit Binary Counters With Individual Clocks
  • Direct Clear for Each 4-Bit Counter
  • Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74LV393A contains eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. This device is designed for 2-V to 5.5-V VCC operation.

This device comprises two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)\ input. The device changes state on the negative-going transition of the CLK\ pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The SN74LV393A has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV393A contains eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. This device is designed for 2-V to 5.5-V VCC operation.

This device comprises two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)\ input. The device changes state on the negative-going transition of the CLK\ pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The SN74LV393A has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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类型 标题 下载最新的英语版本 日期
* 辐射与可靠性报告 SN74LV393ATPWREP Reliability Report 2013年 9月 5日
* 数据表 SN74LV393A-EP 数据表 (Rev. A) 2004年 5月 11日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点