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SN74LV595A-EP

已停产

具有 3 态输出的 8 位移位寄存器（增强型米6体育平台手机版_好二三四）

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SN74LV595A-EP 不再投入量产
此米6体育平台手机版_好二三四不再投入生产。新设计应考虑替代米6体育平台手机版_好二三四。
open-in-new 比较替代米6体育平台手机版_好二三四
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SN74LV595B-EP 正在供货 具有三态输出寄存器的增强型米6体育平台手机版_好二三四八位移位寄存器 Replacement

SN74LV595A-EP

已停产
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米6体育平台手机版_好二三四详情

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 45 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating HiRel Enhanced Product
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 45 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating HiRel Enhanced Product
TSSOP (PW) 16 32 mm² 5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7.4 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • 8-Bit Serial-In, Parallel-Out Shift
  • Ioff Supports Partial-Power-Down Mode Operation
  • Shift Register Has Direct Clear

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7.4 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • 8-Bit Serial-In, Parallel-Out Shift
  • Ioff Supports Partial-Power-Down Mode Operation
  • Shift Register Has Direct Clear

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74LV595A device is an 8-bit shift register designed for 2-V to 5.5-V VCC operation.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR)\ input, serial (SER) input, and a serial output for cascading. When the output-enable (OE)\ input is high, all outputs except QH’ are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV595A device is an 8-bit shift register designed for 2-V to 5.5-V VCC operation.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR)\ input, serial (SER) input, and a serial output for cascading. When the output-enable (OE)\ input is high, all outputs except QH’ are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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类型 标题 下载最新的英语版本 日期
* 辐射与可靠性报告 SN74LV595AIPWREP Reliability Report 2018年 3月 14日
* 数据表 SN74LV595A-EP 数据表 (Rev. B) 2004年 5月 11日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点