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SN74LV8154-EP

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增强型米6体育平台手机版_好二三四，具有三态输出寄存器的双路 16 位二进制计数器

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SN74LV8154-EP

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米6体育平台手机版_好二三四详情

Function Counter Bits (#) 16 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Function Counter Bits (#) 16 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Can Be Used as Two 16 Bit Counters or a Single 32 Bit Counter
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 25 ns at 5 V (RCLK to Y)
  • Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Can Be Used as Two 16 Bit Counters or a Single 32 Bit Counter
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 25 ns at 5 V (RCLK to Y)
  • Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be output at Y0-Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.

A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.

To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be output at Y0-Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.

A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.

To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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类型 标题 下载最新的英语版本 日期
* 数据表 Dual 16 Bit Binary Counters With 3-State Output Registers 数据表 (Rev. A) 2007年 9月 10日
* VID SN74LV8154-EP VID V6206662 2016年 6月 21日

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TSSOP (PW) 20 Ultra Librarian
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  • 引脚镀层/焊球材料
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