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SN74LVTH273-EP

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具有清零功能的 3.3V Abt 八路 D 级触发器（增强型米6体育平台手机版_好二三四）

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SN74LVTH273-EP

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米6体育平台手机版_好二三四详情

Number of channels 8 Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Number of channels 8 Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
SOP (NS) 20 98.28 mm² 12.6 x 7.8
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Supports Unregulated Battery Operation Down to 2.7 V
  • Buffered Clock and Direct-Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Ioff Supports Partial Power-Down-Mode Operation
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Supports Unregulated Battery Operation Down to 2.7 V
  • Buffered Clock and Direct-Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Ioff Supports Partial Power-Down-Mode Operation
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

This octal D-type flip-flop is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct-clear (CLR)\ input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This octal D-type flip-flop is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct-clear (CLR)\ input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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类型 标题 下载最新的英语版本 日期
* 数据表 SN74LVTH273-EP 数据表 (Rev. A) 2006年 5月 22日
* VID SN74LVTH273-EP VID V6204674 2016年 6月 21日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
选择指南 《高级总线接口逻辑器件选择指南》 英语版 2010年 7月 7日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
应用手册 Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
应用手册 LVT-to-LVTH Conversion 1998年 12月 8日
应用手册 LVT Family Characteristics (Rev. A) 1998年 3月 1日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
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