主页 时钟和计时 时钟缓冲器
主页
时钟和计时
时钟缓冲器

SN74SSQEA32882

正在供货

符合 JEDEC SSTE32882 标准且具有地址奇偶校验的 810MHz、28 位至 56 位寄存缓冲器

立即订购
数据表

SN74SSQEA32882

正在供货
数据表 立即订购

米6体育平台手机版_好二三四详情

Function Memory interface Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 810 Number of outputs 60 Output supply voltage (V) 1.35 Core supply voltage (V) 1.35 Features DDR3 register Operating temperature range (°C) 0 to 85 Rating Catalog Output type CMOS Input type CMOS
Function Memory interface Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 810 Number of outputs 60 Output supply voltage (V) 1.35 Core supply voltage (V) 1.35 Features DDR3 register Operating temperature range (°C) 0 to 85 Rating Catalog Output type CMOS Input type CMOS
NFBGA (ZAL) 176 108 mm² 13.5 x 8
  • JEDEC SSTE32882 Compliant
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support
    Stacked DDR3 RDIMMs
  • CKE Powerdown Mode for Optimized System Power Consumption
  • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One
    Differential Clock Pair (CK and CK) and Distributing
    to Four Differential Outputs
  • 1.5V/1.35V CMOS Inputs
  • Checks Parity on Command and Address (CS-Gated) Data Inputs
  • Configurable Driver Strength
  • Uses Internal Feedback Loop
  • APPLICATIONS
    • DDR3 Registered DIMMs up to DDR3-1600
    • DDR3L Registered DIMMs up to DDR3L-1333
    • Single-, Dual- and Quad-Rank RDIMM
  • JEDEC SSTE32882 Compliant
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support
    Stacked DDR3 RDIMMs
  • CKE Powerdown Mode for Optimized System Power Consumption
  • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One
    Differential Clock Pair (CK and CK) and Distributing
    to Four Differential Outputs
  • 1.5V/1.35V CMOS Inputs
  • Checks Parity on Command and Address (CS-Gated) Data Inputs
  • Configurable Driver Strength
  • Uses Internal Feedback Loop
  • APPLICATIONS
    • DDR3 Registered DIMMs up to DDR3-1600
    • DDR3L Registered DIMMs up to DDR3L-1333
    • Single-, Dual- and Quad-Rank RDIMM

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V and on DDR3L registered DIMMs with VDD of 1.35 V.

All inputs are 1.5 V and 1.35 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.

The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the "QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.

The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.

The SN74SSQEA32882 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers.

The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals (DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.

The SN74SSQEA32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.

The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.

Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V and on DDR3L registered DIMMs with VDD of 1.35 V.

All inputs are 1.5 V and 1.35 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.

The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the "QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.

The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.

The SN74SSQEA32882 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers.

The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals (DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.

The SN74SSQEA32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.

The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.

Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.
filter 查找其他 时钟缓冲器
下载 观看带字幕的视频 视频

技术文档

star =有关此米6体育平台手机版_好二三四的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 9
类型 标题 下载最新的英语版本 日期
* 数据表 SSQEA32882 DDR3 Register 数据表 (Rev. B) 2010年 9月 21日
应用手册 半导体和 IC 封装热指标 (Rev. D) PDF | HTML 英语版 (Rev.D) PDF | HTML 2024年 4月 24日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
应用手册 半导体和集成电路 (IC) 封装热度量 (Rev. B) 最新英语版本 (Rev.D) PDF | HTML 2013年 8月 2日
应用手册 Recommendation for Register-Related SPD Settings on DDR3 RDIMM (Rev. B) 2013年 7月 26日
应用手册 Programmable Yn Clock Phase Shift w/SN74SSQEA32882 DDR3 Register 2010年 1月 11日
应用手册 DDR3 Register Input Bus Termination Measurement 2009年 11月 16日
应用手册 CMR Programming for DDR3 Registers 2009年 6月 25日
应用手册 Overview of JEDEC RawCards for DDR3 RDIMM 2008年 9月 19日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源米6体育平台手机版_好二三四系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短米6体育平台手机版_好二三四上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)



发送申请
封装 引脚 CAD 符号、封装和 3D 模型
NFBGA (ZAL) 176 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频