THS8200-EP

Name: THS8200-EP
Brand: TI
SKU: THS8200-EP
Price: 14.96 USD

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三通道 10 位全格式视频 DAC（增强型米6体育平台手机版_好二三四）

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数据表

document-pdfAcrobat All-Format Oversampled Component Video/PC Graphics D/A System 数据表 (英语)

THS8200-EP

正在供货

数据表

立即订购

米6体育平台手机版_好二三四详情

Rating

HiRel Enhanced Product

Supply voltage (V)

3.6

Operating temperature range (°C)

-40 to 85

Rating

HiRel Enhanced Product

Supply voltage (V)

3.6

Operating temperature range (°C)

-40 to 85

HTQFP (PFP)

80

196 mm² 14 x 14

Three 11-Bit 205-MSPS D/A Converters With Integrated
Bi-Level/Tri-Level Sync Insertion
Support for All ATSC Video Formats (Including 1080P) and
PC Graphics Formats (Up to UXGA at 75 Hz)
INPUT
- Flexible 10/15/16/20/24/30-Bit Digital Video Input Interface
  With Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 Sampled
- Video Synchronization Via Hsync, Vsync Dedicated Inputs or Via
  Extraction of Embedded SAV/EAV Codes According to ITU-R.BT601
  (SDTV) or SMPTE274M/SMPTE296M (HDTV)
- Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can Receive
  Video-Over-DVI Formats According to the EIA-861 Specification and
  Convert to YPbPr/RGB Component Formats With Separate Syncs or
  Embedded Composite Sync
VIDEO PROCESSING
- Programmable Clip/Shift/Multiply Function for Operation With
  Full-Range or ITU-R.BT601 Video Range Input Data
- Programmable Digital Fine-Gain Controller on Each Analog Output
  Channel, for Accurate Channel Matching and Programmable
  White-Balance Control
- Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
- Built-In 2× Oversampling SDTV/HDTV Interpolation
  Filter for Improved Video Frequency Characteristic
- Fully Programmable Digital Color Space Conversion Circuit
- Fully Programmable Display Timing Generator to Supply All
  SDTV and HDTV Composite Sync Ttiming Formats, Progressive
  and Interlaced
- Fully Programmable Hsync/Vsync Outputs
- Vertical Blanking Interval (VBI) Override or Data Pass-Thru
  for VBI Data Transparency
- Programmable CGMS Data Generation and Insertion
OUTPUT
- Digital
  - ITU-R BT.656 Digital Video Output Port
- Analog
  - Analog Component Output from Software-Switchable
    700-mV/1.3-V Compliant Output DACs at 37.5- load
  - Programmable Video/Sync Ratio (7:3 or 10:4)
  - Programmable Video Pedestal
GENERAL
- Built-In Video Color Bar Test Pattern Generator
- Fast Mode I²C Control Interface
- Configurable Master or Slave Timing Mode
  - Configuration Modes Allow the Device to Act as a
    Master Timing Source for Requesting Data from, e.g.,
    the Video Frame Buffer. Alternatively, the Device Can
    Slave to an External Timing Master (Master Mode Only
    Available for PC Graphics Output Modes).
- DAC and Chip Powerdown Modes
- Low-Power 1.8-/3.3-V Operation
- 80-pin PowerPAD™ Plastic Quad Flatpack Package with
  Efficient Heat Dissipation and Small Physical Size
APPLICATIONS
- DVD Players
- Digital-TV/Interactive-TV/Internet Set-Top Boxes
- Personal Video Recorders
- HDTV Display or Projection Systems
- digital Video Systems

PowerPAD Is a trademark of Texas Instruments.

Three 11-Bit 205-MSPS D/A Converters With Integrated
Bi-Level/Tri-Level Sync Insertion
Support for All ATSC Video Formats (Including 1080P) and
PC Graphics Formats (Up to UXGA at 75 Hz)
INPUT
- Flexible 10/15/16/20/24/30-Bit Digital Video Input Interface
  With Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 Sampled
- Video Synchronization Via Hsync, Vsync Dedicated Inputs or Via
  Extraction of Embedded SAV/EAV Codes According to ITU-R.BT601
  (SDTV) or SMPTE274M/SMPTE296M (HDTV)
- Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can Receive
  Video-Over-DVI Formats According to the EIA-861 Specification and
  Convert to YPbPr/RGB Component Formats With Separate Syncs or
  Embedded Composite Sync
VIDEO PROCESSING
- Programmable Clip/Shift/Multiply Function for Operation With
  Full-Range or ITU-R.BT601 Video Range Input Data
- Programmable Digital Fine-Gain Controller on Each Analog Output
  Channel, for Accurate Channel Matching and Programmable
  White-Balance Control
- Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
- Built-In 2× Oversampling SDTV/HDTV Interpolation
  Filter for Improved Video Frequency Characteristic
- Fully Programmable Digital Color Space Conversion Circuit
- Fully Programmable Display Timing Generator to Supply All
  SDTV and HDTV Composite Sync Ttiming Formats, Progressive
  and Interlaced
- Fully Programmable Hsync/Vsync Outputs
- Vertical Blanking Interval (VBI) Override or Data Pass-Thru
  for VBI Data Transparency
- Programmable CGMS Data Generation and Insertion
OUTPUT
- Digital
  - ITU-R BT.656 Digital Video Output Port
- Analog
  - Analog Component Output from Software-Switchable
    700-mV/1.3-V Compliant Output DACs at 37.5- load
  - Programmable Video/Sync Ratio (7:3 or 10:4)
  - Programmable Video Pedestal
GENERAL
- Built-In Video Color Bar Test Pattern Generator
- Fast Mode I²C Control Interface
- Configurable Master or Slave Timing Mode
  - Configuration Modes Allow the Device to Act as a
    Master Timing Source for Requesting Data from, e.g.,
    the Video Frame Buffer. Alternatively, the Device Can
    Slave to an External Timing Master (Master Mode Only
    Available for PC Graphics Output Modes).
- DAC and Chip Powerdown Modes
- Low-Power 1.8-/3.3-V Operation
- 80-pin PowerPAD™ Plastic Quad Flatpack Package with
  Efficient Heat Dissipation and Small Physical Size
APPLICATIONS
- DVD Players
- Digital-TV/Interactive-TV/Internet Set-Top Boxes
- Personal Video Recorders
- HDTV Display or Projection Systems
- digital Video Systems

PowerPAD Is a trademark of Texas Instruments.

THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.

THS8200 can accept a variety of digital input formats, in both 4:4:4 and 4:2:2 formats, over a 3×10-bit, 2×10-bit or 1×10-bit interface. The device synchronizes to incoming video data either through dedicated Hsync/Vsync inputs or through extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. Alternatively, when configured for generating PC graphics output, THS8200 also provides a master timing mode in which it requests video data from an external (memory) source.

THS8200 contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully-programmable 3×3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2× oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.

The output compliance range can be set via external adjustment resistors and there is a choice of two settings, in order to accommodate without hardware changes both component video/PC graphics (700 mV) and composite video (1.3 V) outputs. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. In order to avoid nonlinearities after scaling of the video range, the DACs are internally of 11-bit resolution. Furthermore, a bi- or tri-level sync with programmable amplitude (in order to support both 700/300-mV and 714/286-mV video/sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range. This preserves 100% of the DAC’s 11-bit dynamic range for video data.

THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.

THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.

THS8200 can accept a variety of digital input formats, in both 4:4:4 and 4:2:2 formats, over a 3×10-bit, 2×10-bit or 1×10-bit interface. The device synchronizes to incoming video data either through dedicated Hsync/Vsync inputs or through extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. Alternatively, when configured for generating PC graphics output, THS8200 also provides a master timing mode in which it requests video data from an external (memory) source.

THS8200 contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully-programmable 3×3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2× oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.

The output compliance range can be set via external adjustment resistors and there is a choice of two settings, in order to accommodate without hardware changes both component video/PC graphics (700 mV) and composite video (1.3 V) outputs. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. In order to avoid nonlinearities after scaling of the video range, the DACs are internally of 11-bit resolution. Furthermore, a bi- or tri-level sync with programmable amplitude (in order to support both 700/300-mV and 714/286-mV video/sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range. This preserves 100% of the DAC’s 11-bit dynamic range for video data.

THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.

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	类型	标题	日期
*	数据表	All-Format Oversampled Component Video/PC Graphics D/A System 数据表	2009年 12月 3日
*	VID	THS8200-EP VID V6210604	2016年 6月 21日
	应用手册	Noise Analysis for High Speed Op Amps (Rev. A)	2005年 1月 17日

设计和开发

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仿真模型

THS8200 IBIS Model

SLEM013.ZIP (48 KB) - IBIS Model

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模拟工具

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用户指南: PDF

英语版 (Rev.A): PDF

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封装	引脚	CAD 符号、封装和 3D 模型
HTQFP (PFP)	80	Ultra Librarian

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THS8200-EP

三通道 10 位全格式视频 DAC（增强型米6体育平台手机版_好二三四）

THS8200-EP

米6体育平台手机版_好二三四详情

技术文档

设计和开发

THS8200 IBIS Model

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

TINA-TI — 基于 SPICE 的模拟仿真程序

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