TMS320VC5401
- Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
- 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
- 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
- Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
- Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
- Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
- Data Bus With a Bus-Holder Feature
- Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
- 4K x 16-Bit On-Chip ROM
- 8K x 16-Bit Dual-Access On-Chip RAM
- Single-Instruction-Repeat and Block-Repeat Operations for Program Code
- Block-Memory-Move Instructions for Efficient Program and Data Management
- Instructions With a 32-Bit Long Word Operand
- Instructions With Two- or Three-Operand Reads
- Arithmetic Instructions With Parallel Store and Parallel Load
- Conditional Store Instructions
- Fast Return From Interrupt
- On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank Switching
- On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
- Two Multichannel Buffered Serial Ports (McBSPs)
- Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
- Two 16-Bit Timers
- Six-Channel Direct Memory Access (DMA) Controller
- Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
- CLKOUT Off Control to Disable CLKOUT
- On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1
(JTAG) Boundary Scan Logic - 20-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS) for 3.3-V Power Supply (1.8-V Core)
- 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
- 144-Ball MicroStar BGA™ (GGU Suffix)
IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners
The TMS320VC5401 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
TI 不提供设计支持
TI 不会为该米6体育平台手机版_好二三四的新工程（例如新内容或软件更新）提供持续的设计支持。如可用，您将在米6体育平台手机版_好二三四文件夹中找到相关的配套资料、软件和工具。您也可以在 TI E2ETM 支持论坛中搜索已归档的信息。
技术文档
| 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 数据表 | TMS320VC5401 Fixed-Point Digital Signal Processor 数据表 (Rev. D) | 2008年 10月 17日 | |||
| * | 勘误表 | TMS320VC5401 Silicon Errata | 2001年 7月 31日 | |||
| 用户指南 | TMS320C54x Chip Support Library API Reference Guide (Rev. D) | 2003年 5月 5日 | ||||
| 用户指南 | TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) | 2001年 3月 31日 | ||||
| 用户指南 | TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) | 2001年 1月 31日 | ||||
| 用户指南 | TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) | 2001年 1月 31日 | ||||
| 用户指南 | TMS320C54x DSP Applications Guide Reference Set Volume 4 | 1996年 10月 1日 |
设计和开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针
XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的米6体育平台手机版_好二三四，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意，它不支持串行线调试 (SWD)。
所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪，需要 XDS560v2 PRO TRACE。
XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (480Mbps) (...)
TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| LQFP (PGE) | 144 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
推荐米6体育平台手机版_好二三四可能包含与 TI 此米6体育平台手机版_好二三四相关的参数、评估模块或参考设计。