米6体育平台手机版_好二三四详情

DSP type 1 C54x DSP (max) (MHz) 120 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 1 C54x DSP (max) (MHz) 120 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
LQFP (PGE) 144 484 mm² 22 x 22
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus Holder Feature
  • Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
  • On-Chip ROM
    • 128K × 16-Bit (5407) Configured for Program Memory
    • 64K × 16-Bit (5404) Configured for Program Memory
  • On-Chip RAM
    • 40K × 16-Bit (5407) Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
    • 16K x 16-Bit (5404) Composed of Two Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
  • Enhanced External Parallel Interface (XIO2)
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Better Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank-Switching
    • On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
    • Universal Asynchronous Receiver/Transmitter (UART) With Integrated Baud Rate Generator
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 144-Pin Ball Grid Array (BGA) (GGU Suffix)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
  • 3.3-V I/O Supply Voltage
  • 1.5-V Core Supply Voltage

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
All trademarks are the property of their respective owners.
TMS320C54x is a trademark of Texas Instruments.

  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus Holder Feature
  • Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
  • On-Chip ROM
    • 128K × 16-Bit (5407) Configured for Program Memory
    • 64K × 16-Bit (5404) Configured for Program Memory
  • On-Chip RAM
    • 40K × 16-Bit (5407) Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
    • 16K x 16-Bit (5404) Composed of Two Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
  • Enhanced External Parallel Interface (XIO2)
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Better Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank-Switching
    • On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
    • Universal Asynchronous Receiver/Transmitter (UART) With Integrated Baud Rate Generator
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 144-Pin Ball Grid Array (BGA) (GGU Suffix)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
  • 3.3-V I/O Supply Voltage
  • 1.5-V Core Supply Voltage

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
All trademarks are the property of their respective owners.
TMS320C54x is a trademark of Texas Instruments.

This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404 (hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407 and 5404 are essentially the same device except for differences in their memory maps.

This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.

This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404 (hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407 and 5404 are essentially the same device except for differences in their memory maps.

This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320VC5407/TMS320VC5404 Fixed-Point Digital Signal Processors 数据表 (Rev. E) 2008年 10月 20日
用户指南 TMS320C54x Chip Support Library API Reference Guide (Rev. D) 2003年 5月 5日
用户指南 TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) 2001年 3月 31日
用户指南 TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) 2001年 1月 31日
用户指南 TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) 2001年 1月 31日
用户指南 TMS320C54x DSP Applications Guide Reference Set Volume 4 1996年 10月 1日

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调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的米6体育平台手机版_好二三四,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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封装 引脚 CAD 符号、封装和 3D 模型
LQFP (PGE) 144 Ultra Librarian

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包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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