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线性和低压降 (LDO) 稳压器

TPS701

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具有电源正常指示和使能功能的 500mA、双通道低压降稳压器

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TPS7A87 正在供货 500mA、低噪声、高 PSRR、双通道可调节超低压降稳压器 Alternative dual LDO with ultra-low-noise performance in a 4-mm x 4-mm WQFN package.

TPS701

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米6体育平台手机版_好二三四详情

Output options Adjustable Output, Dual output, Fixed Output Iout (max) (A) 0.5 Vin (max) (V) 6 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.2 Fixed output options (V) 1.2, 1.5, 1.8, 2.5, 3.3 Rating Catalog Noise (µVrms) 65 PSRR at 100 KHz (dB) 20 Iq (typ) (mA) 0.19 Thermal resistance θJA (°C/W) 74 Load capacitance (min) (µF) 10 Regulated outputs (#) 2 Features Enable, Output discharge, Power good, Sequencing and monitoring Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 170 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Dual output, Fixed Output Iout (max) (A) 0.5 Vin (max) (V) 6 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.2 Fixed output options (V) 1.2, 1.5, 1.8, 2.5, 3.3 Rating Catalog Noise (µVrms) 65 PSRR at 100 KHz (dB) 20 Iq (typ) (mA) 0.19 Thermal resistance θJA (°C/W) 74 Load capacitance (min) (µF) 10 Regulated outputs (#) 2 Features Enable, Output discharge, Power good, Sequencing and monitoring Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 170 Operating temperature range (°C) -40 to 125
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4
  • Dual Output Voltages for Split-Supply Applications
  • Selectable Power-Up Sequencing for DSP Applications
  • Output Current Range of 500mA on Regulator 1 and 250mA on Regulator 2
  • Fast Transient Response
  • Voltage Options: 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V,
    and Dual Adjustable Outputs
  • Open Drain Power-On Reset with 120ms Delay
  • Open Drain Power Good for Regulator 1
  • Ultra Low 190µA (typ) Quiescent Current
  • 1µA Input Current During Standby
  • Low Noise: 65µVRMS Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • Two Manual Reset Inputs
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 20-Pin PowerPAD™ TSSOP Package
  • Thermal Shutdown Protection

PowerPAD, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
  • Dual Output Voltages for Split-Supply Applications
  • Selectable Power-Up Sequencing for DSP Applications
  • Output Current Range of 500mA on Regulator 1 and 250mA on Regulator 2
  • Fast Transient Response
  • Voltage Options: 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V,
    and Dual Adjustable Outputs
  • Open Drain Power-On Reset with 120ms Delay
  • Open Drain Power Good for Regulator 1
  • Ultra Low 190µA (typ) Quiescent Current
  • 1µA Input Current During Standby
  • Low Noise: 65µVRMS Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • Two Manual Reset Inputs
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 20-Pin PowerPAD™ TSSOP Package
  • Thermal Shutdown Protection

PowerPAD, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.

TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution.

The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors.

These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1µA at TJ = +25°C.

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively.

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (for example, an overload condition), VOUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1.

The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of VOUT2 and both manual reset pins (MR1 and MR2). When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes to the logic low state when the VOUT2 regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2.

The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V.

TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution.

The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors.

These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1µA at TJ = +25°C.

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively.

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (for example, an overload condition), VOUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1.

The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of VOUT2 and both manual reset pins (MR1 and MR2). When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes to the logic low state when the VOUT2 regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2.

The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V.
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类型 标题 下载最新的英语版本 日期
* 数据表 Dual-Output Low-Dropout Vltg Reg with Pwr Up Sequencing For Split Vo 数据表 (Rev. I) 2010年 8月 19日
应用手册 LDO 噪声揭秘 (Rev. B) PDF | HTML 英语版 (Rev.B) PDF | HTML 2020年 9月 16日
应用手册 Using Thermal Calculation Tools for Analog Components (Rev. A) 2019年 8月 30日
应用手册 LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
应用手册 简化的 LDO PSRR 测量 最新英语版本 (Rev.A) PDF | HTML 2010年 7月 28日
应用手册 Power Supply Sequencing Solutions for Dual Supply Voltage DSPs (Rev. A) 2000年 7月 5日
用户指南 Low-Dropout, Dual-Output Line Regulator EVM Using the TPS70151 (Rev. A) 2000年 4月 12日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

参考设计

PMP22510 — 开关型集成电容器降压 (SCIB) 转换器参考设计

该开关电容器集成降压 (SCIB) 转换器经高度优化，适用于高功率、高密度单输出功率转换器。它可在 40V 至 60V 的宽输入电压轨范围内工作，每相可生成 8.0V、5.0V、3.3V 或 1.8V 电压轨及最高 40A 的负载电流。该参考设计在 23mm x 23mm 的 PCB 上集成了 CSD95490Q5MC 和 CSD95379Q3M NexFET MOSFET 功率级、UCC27212 驱动器 IC、电容器和电感器，并可与多相降压控制器 TPS53667 兼容，以实现功率级切换功能。
测试报告: PDF
原理图: PDF
封装 引脚 CAD 符号、封装和 3D 模型
HTSSOP (PWP) 20 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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