The ADS58J64EVM is an evaluation board used to evaluate the ADS58J64 Integrated Receiver from Texas Instruments. The ADS58J64 is a low power, 14-bit, 500-MSPS, quad channel telecom receiver with a buffered analog input. The device supports JESD204B interface and data rates up to 10Gbps. The EVM has transformer coupled analog and clock inputs to support single ended signal and clock sources and also to accommodate a wide range of signal frequencies. The transformers at the analog input are connected back to back for better amplitude and phase matching performance. The on-board clock synthesizer/distribution chip, LMK04828 may be used to provide an ultra-low-jitter and phase noise device clock and matched system reference clocks(SYSREF) for the JESD204B interface of the ADC and data capture board (TSW14J56EVM). The ADS58J64 and LMK04828 are both controlled through an easy to use software Graphic User Interface (GUI).
The ADS58J64EVM can connect directly to the TSW14J56EVM via an FMC connector for data capture and subsequent analyses with the HSDCPRO software. The ADS58J64EVM can also be connected to any FPGA/ASIC evaluation module that includes an FMC connector.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | EVM User's guide | ADS58J64EVM User's Guide | 09 Jan 2017 | |
| Certificate | ADS58J64EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 |
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