CODELOADER
CodeLoader Software for device register programming
CODELOADER
Overview
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | Loop filter & device configuration + simulation | Device register programming |
LMX24xx PLL family | EasyPLL | CodeLoader* |
LMX25xx PLL+VCO family | ||
LMK jitter cleaners and distributors |
*For new designs, use the Clocks and Synthesizers (TICS) Pro Software tool.
Downloads
Additional resources you might need
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
Supported products & hardware
Products
Clock generators
RF PLLs & synthesizers
Clock buffers
Oscillators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.5 installer binary for Windows operating system
Products
Clock generators
RF PLLs & synthesizers
Clock buffers
Oscillators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
Documentation
TICS Pro 1.7.7.5 Release Notes
TICS Pro 1.7.7.5 Software Manifest
Release Information
Added Features
- LMK5B12212, LMK5C22212A support EEPROM programming
Bug Fixes
- LMK3H0102 - No longer writes registers on startup.
- LMK05318B - Export EEPROM Map button bugfix.
- LMK5B/LMK5C family - Small usability bug-fixes.
Known Issues
- LMK5C33216
- When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318
- In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
What's new
- Bugfixes and improvements.
PLLATINUMSIM-SW — PLLatinum Sim Tool
Supported products & hardware
Products
RF PLLs & synthesizers
Clock buffers
Clock generators
IQ demodulators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
PLLATINUMSIM-SW — PLLatinum Sim Tool
Products
RF PLLs & synthesizers
Clock buffers
Clock generators
IQ demodulators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
Documentation
Release Information
Bug fixes
What's new
- Fixed Kvco calculation bug introduced in 1.6.6
- Added warning for loop bandwidth being restricted due to min high order capacitance.
Supported products & hardware
Clock buffers
Clock generators
Clock jitter cleaners
RF PLLs & synthesizers
Evaluation board
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | User guide | CodeLoader 4 Operating Instructions User's Guide (Rev. A) | 21 Jul 2014 | |
Technical article | A survival guide to scaling your PLL loop filter design | PDF | HTML | 22 Nov 2016 | |
Technical article | What to do when your PLL does not lock | PDF | HTML | 12 Jul 2016 |
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.