LMK04832SEPEVM

LMK04832-SEP evaluation module for ultra-low-noise, 3.2-GHz 15-output clock jitter clea

LMK04832SEPEVM

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Overview

The LMK04832-SEP evaluation module (EVM) is a platform to evaluate the performance and features of the LMK04832-SEP, which is a space-grade, ultra-low-noise, JESD204B/C, dual-loop clock jitter cleaner.

The LMK04832-SEP device on each EVM is an engineering model, intended for engineering evaluation only. The device and EVM is not suitable for
qualification, production, radiation testing or flight use.

Features
  • Single-event latch-up (SEL) and single-event functional interrupt (SEFI) immune > 43 MeV.cm2/mg
  • JESD204B/C support for space applications requiring system reference (SYSREF)
  • 6-GHz external voltage-controlled oscillator (VCO) or distribution input
  • Multimode
    • Dual phase-locked loop (PLL)
    • Single PLL
    • Clock distribution
  • Complete circuit for dual-loop clock jitter cleaner, optimized and tested for performance
Clock jitter cleaners
LMK04832-SEP Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner
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Evaluation board

LMK04832SEPEVM

LMK04832-SEP evaluation module for ultra-low-noise, 3.2-GHz 15-output clock jitter cleaner

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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Supported products & hardware
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TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

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Latest version
Version: 1.7.7.6
Release date: 29 Oct 2024
lock TICSPro_1.7.7.6_29-Oct-2024.exe  — 142030 K

TICS Pro 1.7.7.6 installer binary for Windows operating system

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RF PLLs & synthesizers
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Evaluation board
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Documentation

TICS Pro 1.7.7.6 Release Notes

TICS Pro 1.7.7.6 Software Manifest

Release Infomation

Added Features

LMK5Bxxyyy, LMK5Cxxyyy

  • Warnings and errors improved, particularly corrective suggestions
  • REFx_FREQ=0 automatically disables DPLL reference input selection for that input
  • Input validation enabled and disabled by start page settings, including 1PPS
  • APLL reference selection moved to Step 5, just before clock output definition
  • Quick-set multiple outputs to the same settings on frequency planner
  • BAW VCO allows some ppm deviation
  • Force SYSREF option on OUT0/1
  • Expose DPLLx_LCK_TIMER field
  • Match LMK05318B EEPROM page design
  • .EPR export option
  • EEPROM SRAM programming generation support
  • For complete changelist, see release notes

LMK3H0102

  • Configuration search tool
  • Wizard: voltage selection option

Bug Fixes

  • LMK04832-SP, LMK04832-SEP, LMK04714-Q1, LMK04368-EP - PD_FIN0 corrected to FIN0_PD
  • LMK3H0102 - Several wizard bugfixes

Known Issues

  • LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
  • LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
  • Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
  • User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
TI's Standard Terms and Conditions for Evaluation Items apply.

Technical documentation

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Type Title Date
* EVM User's guide LMK04832SEPEVM User’s Guide PDF | HTML 28 Sep 2022
Certificate LMK04832SEPEVM EU RoHS Declaration of Conformity (DoC) 06 Sep 2022

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