This reference design is a demonstration of a SONAR receive-path sub-system using the integrated analog front end (AFE) AFE5809. AFE5809 features eight channels of analog signal conditioning (LNA + VCAT + PGA) and digital processing (ADC + digital demodulator) that brings a high level of system receive-path integration and enables high-performance echo-location imaging for high-end SONAR systems. This reference design demonstrates this SONAR sub-system with a schematic modified from the AFE5809EVM. The test data included is taken by combining AFE5809EVM with TSW1400EVM FPGA capture card and their respective software GUIs in order simulate a receive chain solution capable of high-performance measurement.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | SONAR Receiver Path Sub-System Using the AFE5809 Design Guide | Nov. 23, 2014 |
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