The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.
This design has two ADC12QJ1600-Q1 devices on the same printed circuit board (PCB), which can be used to demonstrate multiple ADC synchronizations, deterministic latency, and test the performance of the ADC with various front-end options (AC-coupled transformer; DC-coupled option with LMH32401). The design also demonstrates how the clocking scheme can be simplified by daisy-chaining the PLL reference output (PLLREFO+, PLLREFO-) from one ADC to another, eliminating the need for the clock-distribution chip that is usually needed by JESD devices.
TSW12QJ1600EVM output data is transmitted over a standard JESD204C high-speed serial interface.
ADC12QJ1600-Q1 and LMH32401 are controlled through an easy-to-use software GUI to enable quick configuration for a variety of uses.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | EVM User's guide | TSW12QJ1600 Evaluation Module User's Guide | 20 Jul 2020 | |
| Certificate | TSW12QJ1600EVM EU Declaration of Conformity (DoC) | 29 Jul 2020 |
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