The TSW14J58 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the TI JESD204B/C family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs), and analog front ends (AFEs).
Populated with a Xilinx® Kintex™ UltraScale+™ field programmable gate array (FPGA) and using JESD204B/C IP solutions, TSW14J58EVM can be dynamically configured to support all lane speeds from 1.6 Gbps to 24.5 Gbps, from 1 to 16 lanes.
Together with high-speed data converter pro software (DATACONVERTERPRO-SW), TSW14J58EVM is a complete system that captures and evaluates data samples from ADC, DAC and AFE EVMs that use JESD204B and/or JESD204C.
If your application does not require lane rates higher than 15 Gbps, consider using TSW14J56EVM for maximum lane rates up to 12.5 Gbps or TSW14J57EVM for maximum lane rates up to 15 Gbps.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | EVM User's guide | TSW14J58EVM JESD204C Data Capture and Pattern Generator Card User's Guide | PDF | HTML | 08 Mar 2021 |
| User guide | High-Speed Data Converter Pro GUI User's Guide (Rev. E) | PDF | HTML | 12 Jun 2023 | |
| Certificate | TSW14J58EVM EU RoHS Declaration of Conformity (DoC) | 16 Mar 2021 |
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The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.