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ADS127L18-FPGA-EXAMPLE-CODE

ADS127L18 example FPGA code

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版本: 1.0.0
发布日期: 2024-11-7
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ADS127L18 example Verilog code  — 0 K

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ADS127L14 — 四通道、同步采样、512kSPS 宽带 24 位 Δ-Σ ADC ADS127L18 — 八通道、同步采样、512kSPS 宽带 24 位 Δ-Σ ADC

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Example FPGA code for ADS127L18 data port

This is an example of how to latch data from the ADS127L18 frame-sync data port that outputs the channel conversion data. The data port is a synchronous, read-only interface with synchronized output clock signals (FSYNC and DCLK) and channel data (DOUTx). This Verilog module captures and splits the continuous 1/2/4/8 lane data (including STATUS and CRC bytes if enabled) into eight separate channels and latches the data between frames.