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Hello, and welcome to the TI Precision Lab, discussing the specifications of the I2C bus and what to look for when selecting a switch that can support the protocol. In this video, we'll discuss the standard bus specifications for I2C, bus capacitance, open-drain architecture in pull-up resistors.

We will start by discussing what the I2C protocol specifications are. Next, we will learn about bus capacitance and what open-drain architecture is and why pull-up resistors are needed. The goals of this video is to understand the I2C bus protocol specifications, open-drain architecture, and how to choose an appropriate signal switch for the job depending on a few factors, such as ON-resistance, ON-capacitance in voltaging current limitations.

This video assumes basic understanding of the I2C communication protocol. For more information on the basics of I2C, watch the video series on training.ti.com or check out the application note, "Understanding the I2C Bus." When choosing the right signal switch for I2C-specific applications, it is important to consider the I2C protocol specifications.

There's a different set of specifications for each of the three bi-directional transfer rates shown-- Standard Mode, Fast Mode, and Fast Mode Plus, which execute clocks speeds of 100 kilobits per second, 400 kilobits per second, and 1 megabits per second respectively. The table shown describes the maximum allowed rise on both SDA and SCL signals, capacitive loading per bus line, and low-level output voltage per I2C protocol specifications.

Note that as the data rate becomes faster, rise time greatly decreases. In Standard Mode, the rise time is 1,000 nanoseconds. This specification reduces by a factor of almost 8 when compared to Fast Mode Plus, which has a rise time of 120 nanoseconds.

When trying to obtain the protocol specifications for I2C, it is important to consider all sources of parasitic capacitances. Sources of capacitance stem from the master, Cmaster, capacitance of each slave device, Cslave, and capacitance of the PCB trace, Cpcb. All of these capacitances combine to make the total bus capacitance Cbus, where Cbus equals Cmaster plus Cslave plus Cpcb.

The total bus capacitance for the signal lines SDA and SCL will increase proportionately with each additional slave device. Every slave device added can contribute tens of peak affairs to Cbus. Eventually, the bus capacitance will be too large and will not be able to support any more slave devices per I2C protocol specifications.

One simple solution to this problem is to have multiple pairs of SDA/SCL buses that can mux to by a master device. This will allow the master device to communicate with more slave devices because the total bus capacitance, Cbus, is split across multiple pairs of SDA/SCL lines.

Note that the mono for a mux contains both ON-resistance, Ron, and ON-capacitance, Con. These will both contribute to the total RC constant, which affects the rise time of the I2C protocol specifications. While this design solution does a fantastic job of allowing more slave device support, the choice of the signal switch can greatly impact the design solution.

Take, for example, this low are Ron switch that has an ON-resistance off 0.26 ohms and an ON-capacitance of 250 picofarads. On the other hand, we have a low ON-capacitance switch, where Ron equals 5.7 ohms, and Con equals 1.4 picofarads. While the first signal switch has a smaller ON-resistance compared to the second signal switch, the ON-capacitance is roughly 178 times greater than that of the second.

Keep in mind that for the Standard Mode transfer rate, the total bus capacitance cannot exceed 400 picofarads. The low Ron switch has taken more than half of the specification, limiting the amount of slave devices that can be added to the bus. The second switch will be able to support many more slave devices due to its low ON-capacitance.

In order to look at the other contributing factors to the I2C protocol specifications, we need to discuss the GPIO pin open-drain with input buffer architecture as common in I2C master slave devices. On the left, we have a master or slave device that demonstrates the open-drain with input buffer architecture. Notice that when the [INAUDIBLE] is turned on, the output of the GPIO pin is pulled to the ground.

However, when the [INAUDIBLE] is turned off, the output of the GPIO pin is left floating. A floating pin can cause unwanted electrical behavior on a device. Since the pin is left unconnected, it acts as a mini antenna, picking up electromagnetic and thermal noise.

To fix the floating pin issue, we simply apply a pull-up resistor to VDD. Now when the [INAUDIBLE] is turned off, the output of the GPIO pin must be pulled up to VDD. The reason to add a pull-up resistor is to eliminate a power-to-ground short and to help drive the signal high through a logic 1. This pull-up resistor, RPU, adds directly to RC time constant, which affects the rise time in the I2C protocol specifications.

Notice from the previous example that the pull-up resistors are connected to ground through the total capacitance of the bus, which is the sum of Cbus plus Con, due to the addition of the signal switch. This is the RC time constant that contributes to the rise time of each bus.

When choosing the correct signal switch for the I2C application, it's important to consider the min and max calculations for the pull-up resistor. Note that the minimum pull-up resistance, Rp(min), is a function of supply voltage, VCC, low level output voltage, VOL, and low level output current, IOL. The absolute maximum range of the signal switch must be able to support the supply voltage in current specifications.

Note that the maximum pull-up, Rp(max), is a function of rise time, tr, and total bus capacitance, Cb. When choosing a signal switch, the ON-capacitance will directly affect this calculation. In summary, there are four key characteristics when choosing a single switch for an I2C protocol-specific application.

1, the supply voltage must be in compliance with the absolute max ratings of the switch. The supply voltage also affects the max pull-up resistance that can be allowed, which directly affects the rise time of the bus. 2, the switch current I-switch must be in compliance with the absolute max current ratings of the switch.

3, every signal switch has some ON-state resistance. This will add directly to the rise time on the bus through the RC time constant. 4, the ON-state capacitance of the switch must be accounted for as this will greatly impact the bus capacitance and rise time specifications of the I2C protocol specifications. ON-state capacitance will also limit the total number of slave devices that the bus can support.

For more details on pull-up resistors and their calculations, check out this application now. You can search our catalog of analog switches and muxes on ti.com, under the switches/multiplexers category. Our Quick Search engine helps to find the right switch for you.

You can filter by configuration, number of channels, or by using the dropdown arrow on the Features tab to find the right signal switch for I2C applications. In this video, you learned about the I2C protocol specifications and what parameters to consider when choosing an appropriate signal switch for I2C-specific applications. Check out our next video on common use cases and muxes with I2C-specific applications.