LMK04805BEVAL
具有双级联 PLL 和集成 2.2 GHz VCO 的时钟抖动消除器
LMK04805BEVAL
概述
The LMK04800 family is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum? architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
特性
- Multi-mode: Dual PLL, single PLL, and clock distribution
- Dual Loop PLLatinum PLL Architecture
- PLL1
> Holdover mode when input clocks are lost
+ Automatic or manual triggering/recovery
- PLL2
> Integrated Low-Noise VCO - 2 redundant input clocks with LOS
- Automatic and manual switch-over modes - 50% duty cycle output divides, 1 to 1045 (even and odd)
- LVPECL, LVDS, or LVCMOS programmable outputs
- Precision digital delay, fixed or dynamically adjustable
- 25 ps step analog delay control.
- 14 differential outputs. Up to 26 single ended.
- Up to 6 VCXO/Crystal buffered outputs - 0-delay mode
Contents:
- Evaluation board
- LPT programming cable (USB interface available separately)
- Quick start sheet
时钟抖动清除器
立即订购并开发
LMK04805BEVAL/NOPB — Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.5 installer binary for Windows operating system
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时钟发生器
射频 PLL 与合成器
时钟缓冲器
振荡器
时钟抖动清除器
时钟网络同步器
硬件开发
评估板
文档
TICS Pro 1.7.7.5 Release Notes
TICS Pro 1.7.7.5 Software Manifest
发布信息
Added Features
- LMK5B12212, LMK5C22212A support EEPROM programming
Bug Fixes
- LMK3H0102 - No longer writes registers on startup.
- LMK05318B - Export EEPROM Map button bugfix.
- LMK5B/LMK5C family - Small usability bug-fixes.
Known Issues
- LMK5C33216
- When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318
- In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
最新信息
- Bugfixes and improvements.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | EVM 用户指南 | LMK0480x Evaluation Board Instructions (Rev. B) | 2014年 8月 4日 | |||
证书 | LMK04805BEVAL/NOPB EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
EVM 用户指南 | LMK048xx Evaluation Board User's Guide | 2013年 11月 26日 | ||||
EVM 用户指南 | LMK0480x Evaluation Board Instructions | 2012年 1月 27日 |