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SNAS466G February 2009 – December 2016 ADC10D1000QML-SP

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

NAA|376

散热焊盘机械数据 (封装 | 引脚)

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snas466g_oa

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Supply voltage (V_A, V_TC, V_DR, V_E)		2.2	V
Supply difference – max(V_A/TC/DR/E) – min(V_A/TC/DR/E)	0	100	mV
Voltage on any input pin (except VinI+, VinI–, VinQ+, VinQ–)	–0.15	(V_A + 0.15)	V
VinI+, VinI–, VinQ+, VinQ– voltage⁽³⁾	–0.5	2.5	V
Input current at VinI+, VinI–, VinQ+, VinQ–⁽⁴⁾		50	mA
Ground difference – max(GND_TC/DR/E) – min(GND_TC/DR/E)	0	100	mV
Input current at any pin⁽⁴⁾		±50	mA
Package power dissipation at T_A ≤ 85°C⁽⁴⁾		3.45	W
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = GND_DR = GND_E = GND_TC = 0 V, unless otherwise specified.

(3) Verified during product qualification high-temperature lifetime testing (HTOL) at T_J = 150°C for 1000 hours continuous operation with
V_A= V_D = 2.2 V.

(4) When the input voltage at any pin exceeds the power supply limits, that is, less than GND or greater than V_A, the current at that pin must be limited to 50 mA. In addition, overvoltage at a pin must adhere to the maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±8000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750
		Machine model	±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Ambient temperature, T_A		–55	125	°C
Supply voltage (V_A, V_TC, V_E)		1.8	2	V
Driver supply voltage (V_DR)		1.8	V_A	V
VinI+, VinI–, VinQ+, VinQ– voltage⁽²⁾	DC-coupled	–0.4	2.4	V
VinI+, VinI–, VinQ+, VinQ– differential voltage⁽³⁾	DC-coupled at 100% duty cycle		1	V
	DC-coupled at 20% duty cycle		2
	DC-coupled at 10% duty cycle		2.8
VinI+, VinI–, VinQ+, VinQ– current⁽²⁾	AC-coupled	–50	50	mA
VinI+, VinI–, VinQ+, VinQ– power	Maintaining common-mode voltage AC-coupled		15.3	dBm
VinI+, VinI–, VinQ+, VinQ– power	Not maintaining common-mode voltage, AC-coupled		17.1	dBm
Ground difference – max(GND_TC/DR/E) – min(GND_TC/DR/E)			0	V
CLK+, CLK– voltage		0	V_A	V
Differential CLK amplitude		0.4	2	V_P-P
V_CMI common-mode input voltage		V_CMO – 150	V_CMO + 150	mV

(1) All voltages are measured with respect to GND = GND_DR = GND_E = GND_TC = 0 V, unless otherwise specified.

(2) Proper common-mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(3) This rating is intended for DC-coupled applications; the voltages and duty cycles listed may be safely applied to V_IN± for the lifetime of the part.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		ADC10D1000QML-SP	UNIT
		NAA (CCGA)
		376 PINS
R_θJA	Junction-to-ambient thermal resistance	13.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	5.0	°C/W
R_θJB	Junction-to-board thermal resistance	5.1	°C/W
ψ_JT	Junction-to-top characterization parameter	2.6	°C/W
ψ_JB	Junction-to-board characterization parameter	4.7	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) Solder process specifications in Board Mounting Recommendation.

6.5 Converter Electrical Characteristics: Static Converter Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q-channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	TYP⁽⁴⁾	MAX	UNIT
INL	Integral non-linearity	DC-coupled, 1-MHz sine wave over-ranged	[1, 2, 3]	±0.7	±1.4	LSB
DNL	Differential non-linearity	DC-coupled, 1-MHz sine wave over-ranged	[1, 2, 3]	±0.2	±0.5	LSB
	Resolution with no missing codes		[1, 2, 3]		10	bits
V_OFF	Offset error			–2.8		LSB
V_{OFF_ADJ}	Input offset adjustment range			±45		mV
PFSE	Positive full-scale error	See⁽⁵⁾	[1, 2, 3]		±28	mV
NFSE	Negative full-scale error	See⁽⁵⁾	[1, 2, 3]		±28	mV
	Out-of-range output code	(V_IN+) − (V_IN−) > + full scale	[1, 2, 3]		1023
	Out-of-range output code	(V_IN+) − (V_IN−) > – full scale	[1, 2, 3]		0

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

(5) Calculation of full-scale error for this device assumes that the actual reference voltage is exactly its nominal value. Full-scale error for this device, therefore, is a combination of full-scale error and reference voltage error. For relationship between gain error and full-scale error, see gain error in Specification Definitions.

6.6 Converter Electrical Characteristics: Dynamic Converter Characteristics

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽⁴⁾	MAX	UNIT
FPBW	Full-power bandwidth	Non-DES mode			2.8		GHz
FPBW	Full-power bandwidth	DES mode			1.3		GHz
CER	Code error rate				10^–18		Error/Sample
	Gain flatness	DC to 498 MHz			±0.25		dBFS
	Gain flatness	DC to 1 GHz			±0.5		dBFS
NPR	Noise power ratio	f_c = 325 MHz, notch width = 25 MHz			47.5		dB
1:2 DEMUX NON-DES MODE, EXTENDED CONTROL MODE, FM (14:0) = 7FFFh
ENOB	Effective number of bits	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]	8.4	9		bits
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	7.8	9
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]	8.2	8.9
		f_IN = 498 MHz, V_IN = –0.5 dBFS,	[6]	7.8	8.9
SINAD	Signal-to-noise plus distortion ratio	f_IN = 248 MHz, V_IN = –0.5 dBFS,	[4, 5]	52.2	55.8		dB
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	48.5	55.8
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]	51	56.8
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]	48.8	56.8
SNR	Signal-to-noise ratio	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]	53.2	56.8		dBc
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	49.4	56.8
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]	52	56.1
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]	49.4	56.1
THD	Total harmonic distortion	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]		–68	–59	dBc
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]		–68	–56
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]		–61	–58
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]		–61	–57
2nd Harm	Second harmonic distortion	f_IN = 248 MHz, V_IN = –0.5 dBFS			−75		dBc
2nd Harm	Second harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			−68		dBc
3rd Harm	Third harmonic distortion	f_IN = 248 MHz, V_IN = –0.5 dBFS			−72		dBc
3rd Harm	Third harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			−67		dBc
SFDR	Spurious-free dynamic range	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]	59	63		dBc
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	53	63
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]	57.5	63
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]	54.5
NON-DEMUX NON-DES MODE, NON-EXTENDED CONTROL MODE, FSR = V_A
ENOB	Effective number of bits	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]	8.1	8.9		bits
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	7.8	8.9
		f_IN = 498 MHz, V_IN = –0.5 dBFS,	[4, 5]	8	8.9
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]	7.7	8.9
SINAD	Signal-to-noise plus distortion ratio	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]	50.3	55.3		dB
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	48.5	55.3
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]	49.8	55.3
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]	48	55.3
SNR	Signal-to-noise ratio	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]	50.9	55.6		dBc
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	49	55.6
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]	50.5	55.9
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]	48.5	55.9
THD	Total harmonic distortion	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]		–67	–59.5	dBc
		f_IN = 248 MHz, V_IN =–0.5 dBFS	[6]		–67	–58.5
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]		–64.3	–58.5
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]		–64.3	–58
2nd Harm	Second harmonic distortion	f_IN = 248 MHz, V_IN = –0.5 dBFS			−75		dBc
2nd Harm	Second harmonic distortion	f_IN = 498 MHz, V_IN = -0.5 dBFS			−68		dBc
3rd Harm	Third harmonic distortion	f_IN = 248 MHz, V_IN = –0.5 dBFS			−72		dBc
3rd Harm	Third harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			−68		dBc
SFDR	Spurious-free dynamic range	f_IN = 248 MHz, V_IN = –0.5 dBFS	[4, 5]	57.5	66.7		dBc
		f_IN = 248 MHz, V_IN = –0.5 dBFS	[6]	53	66.7
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[4, 5]	57.5	66.7
		f_IN = 498 MHz, V_IN = –0.5 dBFS	[6]	54.5	66.7
NON-DEMUX NON-DES MODE, NON-EXTENDED CONTROL MODE, FSR = V_A
ENOB	Effective number of bits	f_IN = 498 MHz, V_IN = –0.5 dBFS			9		bits
SINAD	Signal-to-noise plus distortion ratio	f_IN = 498 MHz, V_IN = –0.5 dBFS			56.2		dB
SNR	Signal-to-noise ratio	f_IN = 498 MHz, V_IN = –0.5 dBFS			56.7		dBc
THD	Total harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			-65.7		dBc
2nd Harm	Second harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			−75		dBc
3rd Harm	Third harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			−68		dBc
SFDR	Spurious-free dynamic range	f_IN = 498 MHz, V_IN = –0.5 dBFS			67.6		dBc
1:4 DEMUX DES MODE (Q-CHANNEL ONLY), ECM, OFFSET/GAIN ADJUSTED ENOB EFFECTIVE NUMBER OF BITS FIN = 498 MHZ, V_IN = –0.5 DBFS
ENOB	Effective number of bits	f_IN = 498 MHz, V_IN = –0.5 dBFS			8.7		bits
SINAD	Signal-to-noise plus distortion ratio	f_IN = 498 MHz, V_IN = –0.5 dBFS			54.2		dB
SNR	Signal-to-noise ratio	f_IN = 498 MHz, V_IN = –0.5 dBFS			55.3		dBc
THD	Total harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			60.7		dBc
2nd Harm	Second harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			−78		dBc
3rd Harm	Third harmonic distortion	f_IN = 498 MHz, V_IN = –0.5 dBFS			−67		dBc
SFDR	Spurious-free dynamic range	f_IN = 498 MHz, V_IN = –0.5 dBFS			63.6		dBc

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

6.7 Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽⁴⁾	MAX	UNIT
V_{IN_FSR}	Analog differential input full-scale range	FSR pin Y3 low	[4, 5, 6]	560	630	680	mV_P-P
		FSR pin Y3 high	[4, 5, 6]	750	820	890	mV_P-P
		EXTENDED CONTROL MODE
		FM(14:0) = 0000h			600		mV_P-P
		FM(14:0) = 4000h (default)			790		mV_P-P
		FM(14:0) = 7FFFh			980		mV_P-P
C_IN	Analog input capacitance, Non-DES mode⁽⁵⁾⁽⁶⁾	Differential			0.02		pF
	Analog input capacitance, Non-DES mode⁽⁵⁾⁽⁶⁾	Each input pin to ground			1.6		pF
	Analog input capacitance, DES mode⁽⁵⁾⁽⁶⁾	Differential			0.08		pF
	Analog input capacitance, DES mode⁽⁵⁾⁽⁶⁾	Each input pin to ground			2.2		pF
R_IN	Differential input resistance		[1, 2, 3]	100	103.5	108	Ω
COMMON-MODE OUTPUT
V_CMO	Common-mode output voltage	I_CMO = ±100 µA	[1, 2, 3]	1.15	1.25	1.35	V
TC_V_CMO	Common-mode output voltage temperature coefficient	I_CMO = ±100 µA			38		ppm/°C
V_{CMO_LVL}	V_CMO input threshold to set DC-coupling mode				0.63		V
C_L_V_CMO	Maximum V_CMO load capacitance	See⁽⁶⁾				80	pF
BANDGAP REFERENCE
V_BG	Bandgap reference output voltage	I_BG = ±100 µA	[1, 2, 3]	1.15	1.25	1.35	V
TC_V_BG	Bandgap reference voltage temperature coefficient	I_BG = ±100 µA			50		ppm/°C
C_LOAD V_BG	Maximum bandgap reference load capacitance				80		pF

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

(5) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22 pF differential and 1.06 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

(6) This parameter is ensured by design and/or characterization and is not tested in production.

6.8 Converter Electrical Characteristics: Channel-to-Channel Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	TYP⁽⁴⁾	UNIT
	Offset match		2	LSB
	Positive full-scale match	Zero offset selected in control register	2	LSB
	Negative full-scale match	Zero offset selected in control register	2	LSB
	Phase matching (I, Q)	f_IN = 1 GHz	< 1	Degree
X-TALK Q-channel	Crosstalk from I channel (aggressor) to Q-channel (victim)	Aggressor = 498 MHz F.S. Victim = 100 MHz F.S.	−61	dB
X-TALK I channel	Crosstalk from Q-channel (aggressor) to I channel (victim)	Aggressor = 498 MHz F.S. Victim = 100 MHz F.S.	−61	dB

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

6.9 Converter Electrical Characteristics: LVDS CLK Input Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽⁴⁾	MAX	UNIT
V_{IN_CLK}	Differential clock input level	Sine wave clock	[1, 2, 3]	0.4	0.6	2	V_P-P
V_{IN_CLK}	Differential clock input level	Square wave clock	[1, 2, 3]	0.4	0.6	2	V_P-P
C_{IN_CLK}	Sampling clock input capacitance⁽⁵⁾⁽⁶⁾	Differential			0.1		pF
C_{IN_CLK}	Sampling clock input capacitance⁽⁵⁾⁽⁶⁾	Each input to ground			1		pF
R_{IN_CLK}	Sampling clock input resistance				100		Ω

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

(5) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22-pF differential and 1.06 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

(6) This parameter is ensured by design and/or characterization and is not tested in production.

6.10 Electrical Characteristics: AutoSync Feature

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽⁴⁾	MAX	UNIT
V_{IN_RCLK}	Differential RCLK input level	Differential peak-to-peak			360		mV_P-P
C_{IN_RCLK}	RCLK input capacitance	Differential			0.1		pF
C_{IN_RCLK}	RCLK input capacitance	Each input to ground			1		pF
R_{IN_RCLK}	RCLK differential input resistance				100		Ω
I_{IH_RCLK}	Input leakage current	V_IN = V_A	[1, 2, 3]	–6		6	µA
I_{IL_RCLK}	Input leakage current	V_IN = GND	[1, 2, 3]	–6		6	µA
V_{O_RCOUT}	Differential RCOut output voltage				360		mV

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽⁴⁾	MAX	UNIT
DIGITAL CONTROL PINS (DES, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS— unless otherwise specified)
V_IH	Logic high input voltage		[1, 2, 3]	0.7 × V_A			V
V_IL	Logic low input voltage		[1, 2, 3]			0.3 × V_A	V
I_IH	Input leakage current	V_IN = V_A	[1, 2, 3]	–6		–0.1	µA
I_IL	Input leakage current (DES, CAL, TPM, FSR, DDRPh)	V_IN = GND	[1, 2, 3]	–6		–0.1	µA
	Input leakage current (SCLK, SDI, SCS)		[1, 2, 3]	–33		–18	µA
	Input leakage current (PDI, PDQ, ECE,)		[1, 2, 3]	–66		–36	µA
C_{IN_DIG}	Input capacitance⁽⁴⁾⁽⁵⁾	Each input to ground			1.5		pF
LVDS OUTPUT PINS (DATA, DCLKI, DCLKQ, ORI, ORQ)
V_OD	LVDS differential output voltage	V_BG = Floating, OVS = High	[1, 2, 3]	300	520	700	mV_P-P
		V_BG = Floating, OVS = Low		160	374	540
		V_BG = V_A, OVS = High		340	568	760
		V_BG = V_A, OVS = Low		190	400	600
ΔV_{O DIFF}	Change in LVDS output swing between logic levels				±1		mV
V_OS	Output offset voltage	V_BG = Floating			0.8		V
V_OS	Output offset voltage	V_BG = V_A			1.2		V
ΔV_OS	Change in output offset voltage between logic levels				±1		mV
I_OS	Output short-circuit current	V_BG = Floating; D+ and D− connected to 0.8 V			±3.8		mA
Z_O	Differential output impedance				100		Ω
DIFFERENTIAL DCLK RESET PINS (DCLK_RST)
V_{CMI_DRST}	DCLK_RST common mode input voltage				1.25 ± 0.15		V
V_{ID_DRST}	Differential DCLK_RST input voltage				0.6		V_P-P
R_{IN_DRST}	Differential DCLK_RST input resistance⁽⁴⁾				100		Ω
DIGITAL OUTPUT PINS (CalRun, SDO)
V_OH	Logic high output level	CalRun, SDO I_OH = –400 µA	[1, 2, 3]	1.5	1.65		V
V_OL	Logic low output level	CalRun, SDO I_OH = 400 µA	[1, 2, 3]		0.15	0.3	V

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

(5) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

6.12 Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode)

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	TYP⁽⁴⁾	MAX	UNIT
I_A	Analog supply current	PDI = PDQ = Low		890		mA
		PDI = Low; PDQ = High		505		mA
		PDI = High; PDQ = Low		505		mA
		PDI = PDQ = High		2		mA
I_TC	Track-and-hold and clock supply current	PDI = PDQ = Low		358		mA
		PDI = Low; PDQ = High		220		mA
		PDI = High; PDQ = Low		220		mA
		PDI = PDQ = High		1		mA
I_DR	Output driver supply current	PDI = PDQ = Low		210		mA
		PDI = Low; PDQ = High		111		mA
		PDI = High; PDQ = Low		111		mA
		PDI = PDQ = High		10		µA
I_E	Digital encoder supply current	PDI = PDQ = Low		60		mA
		PDI = Low; PDQ = High		30.5		mA
		PDI = High; PDQ = Low		30.5		mA
		PDI = PDQ = High		10		µA
P_C	Power consumption	PDI = PDQ = Low	[1, 2, 3]	2.9	3.22	W
		PDI = Low; PDQ = High		1.64	1.88	W
		PDI = High; PDQ = Low		1.64	1.88	W
		PDI = PDQ = High		6		mW

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

6.13 Converter Electrical Characteristics: AC Electrical Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽⁴⁾	MAX	UNIT
INPUT CLOCK (CLK)
f_{CLK (max)}	Maximum input clock frequency		[9, 10, 11]			1	GHz
f_{CLK (min)}	Minimum input clock frequency	Non-DES mode	[9, 10, 11]	200			MHz
f_{CLK (min)}	Minimum input clock frequency	DES mode	[9, 10, 11]		250		MHz
	Input clock duty cycle	f_{CLK (min)} ≤ f_CLK ≤ f_{CLK (max)}		20	50	80	%
t_CL	Input clock low time			200	500		ps
t_CH	Input clock high time			200	500		ps
	DCLK duty cycle				50		%
	DCLK duty cycle				50		%
DCLK_RST
t_SR	Setup time DCLK_RST±				45		ps
t_HR	Hold time DCLK_RST±				45		ps
t_PWR	Pulse Width DCLK_RST±				5		Input Clock Cycles
DATA CLOCK (DCLKI, DCLKQ)
t_{SYNC_DLY}	DCLK synchronization delay	90° mode			4		Input Clock Cycles
t_{SYNC_DLY}	DCLK synchronization delay	0° mode			5
t_LHT	Differential low-to-high transition time	10% to 90%, C_L = 2.5 pF			220		ps
t_HLT	Differential high-to-low transition time	10% to 90%, C_L = 2.5 pF			220		ps
t_SU	Data-to-DCLK set-up time	DDR mode, 90° DCLK			850		ps
t_H	DCLK-to-data hold time	DDR mode, 90° DCLK			850		ps
t_OSK	DCLK-to-data output skew	50% of DCLK transition to 50% of data transition			±75		ps
	DCLK duty cycle				50		%
	DCLK duty cycle				50		%
DATA INPUT-TO-OUTPUT
t_AD	Sampling (aperture) delay	Input CLK+ fall to acquisition of data			1.1		ns
t_AJ	Aperture jitter				0.2		ps (rms)
t_OD	Input clock-to data output delay (in addition to t_LAT)	50% of input clock transition to 50% of data transition			2.4		ns
t_LAT	Latency in 1:2 demux non-DES mode⁽⁵⁾	DI, DQ outputs	[4, 5, 6]	34		34	Input Clock Cycles
	Latency in 1:2 demux non-DES mode⁽⁵⁾	DId, DQd outputs	[4, 5, 6]	35		35	Input Clock Cycles
	Latency in 1:4 demux DES mode⁽⁵⁾	DI outputs	[4, 5, 6]	34		34	Input Clock Cycles
		DQ outputs		34.5		34.5
		DId outputs		35		35
		DQd Outputs		35.5		35.5
	Latency in non-demux non-DES mode⁽⁵⁾	DI outputs	[4, 5, 6]	34		34	Input Clock Cycles
	Latency in non-demux non-DES mode⁽⁵⁾	DQ outputs	[4, 5, 6]	34		34	Input Clock Cycles
	Latency in non-demux DES mode⁽⁵⁾	DI outputs	[4, 5, 6]	34		34	Input Clock Cycles
	Latency in non-demux DES mode⁽⁵⁾	DQ outputs	[4, 5, 6]	34.5		34.5	Input Clock Cycles
t_ORR	Over-range recovery time	Differential V_IN step from ±1.2 V to 0 V to get accurate conversion			1		Input Clock Cycle
t_WU	PD low-to-rated accuracy conversion (wake-up time)	Non-DES mode			500		ns
t_WU	PD low-to-rated accuracy conversion (wake-up time)	DES mode			1		µs

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

(5) This parameter is ensured by design and/or characterization and is not tested in production.

6.14 Timing Requirements: Serial Port Interface

over operating free-air temperature range (unless otherwise noted)
The following specifications apply after calibration for V_A = V_DR = V_TC = V = 1.9 V; I-channel and Q-channel AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	NOM⁽⁴⁾	UNIT
f_SCLK	Serial clock frequency	See⁽⁵⁾			15	MHz
	Serial clock low time		[9, 10, 11]	30		ns
	Serial clock high time		[9, 10, 11]	30		ns
t_SSU	Serial data-to-serial clock rising setup time	See⁽⁵⁾			2.5	ns
t_SH	Serial data-to-serial clock rising hold time	See⁽⁵⁾			1	ns
t_SCS	SCS-to-serial clock rising setup time				2.5	ns
t_HCS	SCS-to-serial clock falling hold time				1.5	ns
t_BSU	Bus turnaround time				10	ns

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

6.15 Timing Requirements: Calibration

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	MAX	UNIT
t_CAL	Calibration cycle time	Non-ECM			2.4 × 10⁷	Clock Cycles
		ECM CSS = 0b			2.3 × 10⁷	Clock Cycles
		ECM; CSS = 1b
		CMS(1:0) = 00b			0.8 × 10⁷	Clock Cycles
		CMS(1:0) = 01b			1.5 × 10⁷
		CMS(1:0) = 10b (ECM default)			2.4 × 10⁷
t_{CAL_L}	CAL pin low time	See⁽⁴⁾	[9, 10,11]	1280		Clock Cycles
t_{CAL_H}	CAL pin high time	See⁽⁴⁾	[9, 10, 11]	1280		Clock Cycles

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC10D1000QML-SP 30071804.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

6.16 Quality Conformance Inspection

MIL-STD-883, Method 5005 - Group A

SUBGROUP	DESCRIPTION	TEMPERATURE (°C)
1	Static tests at	25
2	Static tests at	125
3	Static tests at	–55
4	Dynamic tests at	25
5	Dynamic tests at	125
6	Dynamic tests at	–55
7	Functional tests at	25
8A	Functional tests at	125
8B	Functional tests at	–55
9	Switching tests at	25
10	Switching tests at	125
11	Switching tests at	–55
12	Setting time at	25
13	Setting time at	125
14	Setting time at	–55

6.17 Timing Diagrams

Figure 1. Clocking in 1:4 Demux DES Mode

Figure 2. Clocking in 1:2 Demux Non-DES Mode*

* The timing here is shown for the I channel only. However, the Q channel functions precisely the same as the I channel, with VinQ+, VinQ–, DCLKQ+, DCLKQ–, DQd and DQ instead of VinI+, VinI–, DCLKI+, DCLKI–, DId and DI. Both the I channel and the Q channel use the same CLK+, CLK–.

Figure 3. Clocking in Non-Demux Mode Non-DES Mode**

** The timing here is shown for the Q channel only. However, for the non-demux non-DES node, either the I channel and the Q channel may be used as input. For this case, the I-channel functions precisely the same as those of the Q channel, with VinI+, VinI–, DCLKI+, DCLKI–, and DI instead of VinQ+, VinQ–, DCLKQ+, DCLKQ–, and DQ. Both the I channel and Q channel use the same CLK+, CLK–.

Figure 4. Clocking in Non-Demux Mode DES Mode

Figure 5. Data Clock Reset Timing

Figure 6. On-Command Calibration Timing

Figure 7. Serial Interface Timing

6.18 Typical Characteristics

V_A= V_DR = V_TC = V_E = 1.9 V, f_CLK = 1000 MHz, f_IN = 498 MHz, T_A= 25°C, I channel and Q channel, unused channel terminated to AC ground and 1:2 demux non-DES mode (1:1 demux mode has similar performance), unless otherwise stated. NPR plots Notch f_C = 325 MHz and Notch width = 25 MHz.