The dual-edge sampling (DES) pin selects whether the ADC12D1620 is in DES mode (logic-high) or non-DES mode (logic-low). DES mode means that a single analog input is sampled by both I and Q channels in a time-interleaved manner. One of the ADCs samples the input signal on the rising sampling clock edge (duty cycle corrected); the other ADC samples the input signal on the falling sampling clock edge (duty cycle corrected). In non-ECM, only the I input may be used for DES mode, also known as DESI mode. In ECM, the Q input may be selected through the DEQ bit of the Configuration Register (Addr: 0h; Bit: 6), also known as DESQ mode. In ECM, both the I and Q inputs may be selected, also known as DESIQ or DESCLKIQ mode.

To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See DES/Non-DES Mode for more information.