The ADC12D1620 device can operate in dual-edge sampling (DES) or non-DES mode. In non-DES mode, inputs are sampled at the sampling clock frequency. Depending on whether channels are powered down, one or two inputs may be sampled. The DES mode enables a single analog input to be sampled by both I and Q channels. One channel samples the input on the rising edge of the sampling clock and the other samples the input signal on the falling edge of the sampling clock. A single input is thus sampled twice per clock cycle, resulting in an overall sample rate of twice the sampling clock frequency. Because DES mode uses both I and Q channels to process the input signal, both channels must be powered up for the DES mode to function properly.

See Dual-Edge Sampling Pin (DES) for information on how to select the DES mode. In non-ECM only the I input may be used for the DES mode input. In ECM, either the I or Q input may be selected by first using the DES bit (Addr: 0h; Bit: 7) to select the DES mode. Setting the DEQ bit (Addr: 0h; Bit: 6) selects the Q input, while leaving the default value of DEQ=0 selects the I input.

Two other DES modes are available. These provide improved input bandwidth compared to DESI and DESQ modes, but require driving the I and Q inputs with identical in-phase signals.

The DESIQ mode is selected by setting the DIQ bit (Addr: 0h; Bit: 5). In this mode the I and Q input signals are connected to the I and Q converter channels and also connected to each other internally to enable better I to Q signal matching compared with the DESCLKIQ mode discussed next.

DESCLKIQ mode is similar to the DESIQ mode, except that the I and Q channels remain electrically separate internal to the ADC12D1620. For this reason, the I to Q signal matching is slightly worse, and spurious performance is degraded compared to DESIQ mode. DESCLKIQ input bandwidth is slightly better than the DESIQ bandwidth. The DCK bit (Addr: Eh; Bit: 6) is used to select the 180° sampling-clock mode.

Table 7-7 summarizes the relative bandwidth and SFDR performance of the DES sampling modes:

In the DES mode, the output data must be carefully interleaved in order to reconstruct the sampled signal. If the device is programmed into the 1:4 demux DES mode, the data is effectively demultiplexed by 1:4. If the sampling clock is 1600 MHz, the effective sampling rate is doubled to 3.2 GSPS, and each of the 4 output buses has an output rate of 800 MSPS. All data is available in parallel. To properly reconstruct the sampled waveform, the four words of parallel data that are output with each DCLK must be correctly interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI (see Figure 6-3). If the device is programmed into the nondemux DES mode, two words of parallel data are output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ, DI (see Figure 6-4).