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SNAS500Q May 2010 – May 2017 ADC12D1800

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

NXA|292
- MPBGAB2

散热焊盘机械数据 (封装 | 引脚)

订购信息

3 Pin Configuration and Functions

NXA Package
292-Pin BGA
Top-View

ADC12D1800 30123201.gif

The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Section 4.4 for more information.

3.1 Pin Attributes

Table 3-1 Pin Attributes — Analog Front-End and Clock Balls

PIN NO.	NAME	EQUIVALENT CIRCUIT	DESCRIPTION
H1 J1 N1 M1	VinI+ VinI- VinQ+ VinQ-		Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input. In Extended Control Mode (ECM), the Q-input may optionally be selected for conversion in DES Mode by the DEQ Bit (Addr: 0h, Bit 6). Each I- and Q-channel input has an internal common mode bias that is disabled when DC-coupled Mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the V_CMO Pin. In Non-ECM, the full-scale range of these inputs is determined by the FSR Pin; both I- and Q-channels have the same full-scale input range. In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set via the Control Register (Addr: 3h and Addr: Bh). The input offset may also be adjusted in ECM.
U2 V1	CLK+ CLK-		Differential Converter Sampling Clock. In the Non-DES Mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES Mode, the selected input is sampled on both transitions of this clock. This clock must be AC-coupled.
V2 W1	DCLK_RST+ DCLK_RST-		Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC12D1800s in order to synchronize them with other ADC12D1800s in the system. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync.
C2	V_CMO		Common Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be held at logic-low level. This pin is capable of sourcing/ sinking up to 100 µA. For DC-coupled operation, this pin should be left floating or terminated into high-impedance. In DC-coupled Mode, this pin provides an output voltage which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer.
B1	V_BG		Bandgap Voltage Output or LVDS Common-mode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing/sinking 100 uA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the 1.2V LVDS common-mode voltage is selected; 0.8V is the default.
C3 D3	Rext+ Rext-		External Reference Resistor terminals. A 3.3 kΩ ±0.1% resistor should be connected between Rext+/-. The Rext resistor is used as a reference to trim internal circuits which affect the linearity of the converter; the value and precision of this resistor should not be compromised.
C1 D2	Rtrim+ Rtrim-		Input Termination Trim Resistor terminals. A 3.3 kΩ ±0.1% resistor should be connected between Rtrim+/-. The Rtrim resistor is used to establish the calibrated 100Ω input impedance of VinI, VinQ and CLK. These impedances may be fine tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not ensured for such an alternate value.
E2 F3	Tdiode+ Tdiode-		Temperature Sensor Diode Positive (Anode) and Negative (Cathode) Terminals. This set of pins is used for die temperature measurements. It has not been fully characterized.
Y4 W5	RCLK+ RCLK-		Reference Clock Input. When the AutoSync feature is active, and the ADC12D1800 is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM via Control Register (Addr: Eh).
Y5 U6 V6 V7	RCOut1+ RCOut1- RCOut2+ RCOut2-		Reference Clock Output 1 and 2. These signals provide a reference clock at a rate of CLK/4, when enabled, independently of whether the ADC is in Master or Slave Mode. They are used to drive the RCLK of another ADC12D1800, to enable automatic synchronization for multiple ADCs (AutoSync feature). The impedance of each trace from RCOut1 and RCOut2 to the RCLK of another ADC12D1800 should be 100Ω differential. Having two clock outputs allows the auto-synchronization to propagate as a binary tree. Use the DOC Bit (Addr: Eh, Bit 1) to enable/ disable this feature; default is disabled.

Table 3-2 Pin Attributes — Control and Status Balls

PIN NO.	NAME	EQUIVALENT CIRCUIT	DESCRIPTION
V5	DES		Dual Edge Sampling (DES) Mode select. In the Non-Extended Control Mode (Non-ECM), when this input is set to logic-high, the DES Mode of operation is selected, meaning that the VinI input is sampled by both channels in a time-interleaved manner. The VinQ input is ignored. When this input is set to logic-low, the device is in Non-DES Mode, i.e. the I- and Q-channels operate independently. In the Extended Control Mode (ECM), this input is ignored and DES Mode selection is controlled through the Control Register by the DES Bit (Addr: 0h, Bit 7); default is Non-DES Mode operation.
V4	CalDly		Calibration Delay select. By setting this input logic-high or logic-low, the user can select the device to wait a longer or shorter amount of time, respectively, before the automatic power-on self-calibration is initiated. This feature is pin-controlled only and is always active during ECM and Non-ECM.
D6	CAL		Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of t_{CAL_H} after having held it low a minimum of t_{CAL_L}. If this input is held high at the time of power-on, the automatic power-on calibration cycle is inhibited until this input is cycled low-then-high. This pin is active in both ECM and Non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration.
B5	CalRun		Calibration Running indication. This output is logic-high while the calibration sequence is executing. This output is logic-low otherwise.
U3 V3	PDI PDQ		Power Down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q-channel. Setting either input to logic-low brings the respective I- or Q-channel to an operational state after a finite time delay. This pin is active in both ECM and Non-ECM. In ECM, each Pin is logically OR'd with its respective Bit. Therefore, either this pin or the PDI and PDQ Bit in the Control Register can be used to power-down the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively.
A4	TPM		Test Pattern Mode select. With this input at logic-high, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the ECM, this input is ignored and the Test Pattern Mode can only be activated through the Control Register by the TPM Bit (Addr: 0h, Bit 12).
A5	NDM		Non-Demuxed Mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-Demuxed Mode. Setting this input to logic-low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and Non-ECM.
Y3	FSR		Full-Scale input Range select. In Non-ECM, this input must be set to logic-high; the full-scale differential input range for both I- and Q-channel inputs is set by this pin. In the ECM, this input is ignored and the full-scale range of the I- and Q-channel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. Note that the logic-high FSR value in Non-ECM corresponds to the minimum allowed selection in ECM.
W4	DDRPh		DDR Phase select. This input, when logic-low, selects the 0° Data-to-DCLK phase relationship. When logic-high, it selects the 90° Data-to-DCLK phase relationship, i.e. the DCLK transition indicates the middle of the valid data outputs. This pin only has an effect when the chip is in 1:2 Demuxed Mode, i.e. the NDM pin is set to logic-low. In ECM, this input is ignored and the DDR phase is selected through the Control Register by the DPS Bit (Addr: 0h, Bit 14); the default is 0° Mode.
B3	ECE		Extended Control Enable bar. Extended feature control through the SPI interface is enabled when this signal is asserted (logic-low). In this case, most of the direct control pins have no effect. When this signal is de-asserted (logic-high), the SPI interface is disabled, all SPI registers are reset to their default values, and all available settings are controlled via the control pins.
C4	SCS		Serial Chip Select bar. In ECM, when this signal is asserted (logic-low), SCLK is used to clock in serial data which is present on SDI and to source serial data on SDO. When this signal is de-asserted (logic-high), SDI is ignored and SDO is in TRI-STATE.
C5	SCLK		Serial Clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logic-low, as long as timing specifications are not violated when the clock is enabled or disabled.
B4	SDI		Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low).
A3	SDO		Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is at TRI-STATE when SCS is de-asserted.
D1, D7, E3, F4, W3, U7	DNC	NONE	Do Not Connect. These pins are used for internal purposes and should not be connected, i.e. left floating. Do not ground.
C7	NC	NONE	Not Connected. This pin is not bonded and may be left floating or connected to any potential.

Table 3-3 Pin Attributes — Power and Ground Balls

PIN NO.	NAME	EQUIVALENT CIRCUIT	DESCRIPTION
A2, A6, B6, C6, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6	V_A	NONE	Power Supply for the Analog circuitry. This supply is tied to the ESD ring. Therefore, it must be powered up before or with any other supply.
G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4	V_TC	NONE	Power Supply for the Track-and-Hold and Clock circuitry.
A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15	V_DR	NONE	Power Supply for the Output Drivers.
A8, B9, C8, V8, W9, Y8	V_E	NONE	Power Supply for the Digital Encoder.
J4, K2	VbiasI	NONE	Bias Voltage I-channel. This is an externally decoupled bias voltage for the I-channel. Each pin should individually be decoupled with a 100 nF capacitor via a low resistance, low inductance path to GND.
L2, M4	VbiasQ	NONE	Bias Voltage Q-channel. This is an externally decoupled bias voltage for the Q-channel. Each pin should individually be decoupled with a 100 nF capacitor via a low resistance, low inductance path to GND.
A1, A7, B2, B7, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, H8:N13	GND	NONE	Ground Return for the Analog circuitry.
F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1	GND_TC	NONE	Ground Return for the Track-and-Hold and Clock circuitry.
A13, A17, A20, D13, D16, E17, F17, F20, M17, M20, U13, U17, V18, Y13, Y17, Y20	GND_DR	NONE	Ground Return for the Output Drivers.
A9, B8, C9, V9, W8, Y9	GND_E	NONE	Ground Return for the Digital Encoder.

Table 3-4 Pin Attributes — High-Speed Digital Outputs

PIN NO.	NAME	EQUIVALENT CIRCUIT	DESCRIPTION
K19 K20 L19 L20	DCLKI+ DCLKI- DCLKQ+ DCLKQ-		Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode or Non-Demux Mode, this signal is at ¼ or ½ the sampling clock rate, respectively. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized.
K17 K18 L17 L18	ORI+ ORI- ORQ+ ORQ-		Out-of-Range Output for the I- and Q-channel. This differential output is asserted logic-high while the over- or under-range condition exists, i.e. the differential signal at each respective analog input exceeds the full-scale value. Each OR result refers to the current Data, with which it is clocked out. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver.
J18 J19 H19 H20 H17 H18 G19 G20 G17 G18 F18 F19 E19 E20 D19 D20 D18 E18 C19 C20 B19 B20 B18 C17 · M18 M19 N19 N20 N17 N18 P19 P20 P17 P18 R18 R19 T19 T20 U19 U20 U18 T18 V19 V20 W19 W20 W18 V17	DI11+ DI11- DI10+ DI10- DI9+ DI9- DI8+ DI8- DI7+ DI7- DI6+ DI6- DI5+ DI5- DI4+ DI4- DI3+ DI3- DI2+ DI2- DI1+ DI1- DI0+ DI0- · DQ11+ DQ11- DQ10+ DQ10- DQ9+ DQ9- DQ8+ DQ8- DQ7+ DQ7- DQ6+ DQ6- DQ5+ DQ5- DQ4+ DQ4- DQ3+ DQ3- DQ2+ DQ2- DQ1+ DQ1- DQ0+ DQ0-		I- and Q-channel Digital Data Outputs. In Non-Demux Mode, this LVDS data is transmitted at the sampling clock rate. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data, i.e. the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver.
A18 A19 B17 C16 A16 B16 B15 C15 C14 D14 A14 B14 B13 C13 C12 D12 A12 B12 B11 C11 C10 D10 A10 B10 · Y18 Y19 W17 V16 Y16 W16 W15 V15 V14 U14 Y14 W14 W13 V13 V12 U12 Y12 W12 W11 V11 V10 U10 Y10 W10	DId11+ DId11- DId10+ DId10- DId9+ DId9- DId8+ DId8- DId7+ DId7- DId6+ DId6- DId5+ DId5- DId4+ DId4- DId3+ DId3- DId2+ DId2- DId1+ DId1- DId0+ DId0- · DQd11+ DQd11- DQd10+ DQd10- DQd9+ DQd9- DQd8+ DQd8- DQd7+ DQd7+- DQd6+ DQd6- DQd5+ DQd5- DQd4+ DQd4- DQd3+ DQd3- DQd2+ DQd2- DQd1+ DQd1- DQd0+ DQd0-		Delayed I- and Q-channel Digital Data Outputs. In Non-Demux Mode, these outputs are at TRI-STATE. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the non-delayed data, i.e. the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver.

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