SNAS500Q May   2010  – May 2017 ADC12D1800

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 4.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 4.7  Converter Electrical Characteristics: Analog Input and Output and Reference Characteristics
    8. 4.8  Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics
    9. 4.9  Converter Electrical Characteristics: Sampling Clock Characteristics
    10. 4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics
    11. 4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 4.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 4.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 4.14 Converter Timing Requirements: Serial Port Interface
    15. 4.15 Converter Switching Characteristics: Calibration
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. 5.3.1.1 AC/DC-coupled Mode
        2. 5.3.1.2 Input Full-Scale Range Adjust
        3. 5.3.1.3 Input Offset Adjust
        4. 5.3.1.4 DES Timing Adjust
        5. 5.3.1.5 Sampling Clock Phase (Aperture) Delay Adjust
      2. 5.3.2 Output Control and Adjust
        1. 5.3.2.1 DDR Clock Phase
        2. 5.3.2.2 LVDS Output Differential Voltage
        3. 5.3.2.3 LVDS Output Common-Mode Voltage
        4. 5.3.2.4 Output Formatting
        5. 5.3.2.5 Test Pattern Mode
        6. 5.3.2.6 Time Stamp
      3. 5.3.3 Calibration Feature
        1. 5.3.3.1 Calibration Control Pins and Bits
        2. 5.3.3.2 How to Execute a Calibration
        3. 5.3.3.3 Power-on Calibration
        4. 5.3.3.4 On-Command Calibration
        5. 5.3.3.5 Calibration Adjust
        6. 5.3.3.6 Read/Write Calibration Settings
        7. 5.3.3.7 Calibration and Power-Down
        8. 5.3.3.8 Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES/Non-DES Mode
      2. 5.4.2 Demux/Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. 5.5.1.1 Non-Extended Control Mode
          1. 5.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 5.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 5.5.1.1.3  Dual Data Rate Phase Pin (DDRPh)
          4. 5.5.1.1.4  Calibration Pin (CAL)
          5. 5.5.1.1.5  Calibration Delay Pin (CalDly)
          6. 5.5.1.1.6  Power Down I-channel Pin (PDI)
          7. 5.5.1.1.7  Power Down Q-channel Pin (PDQ)
          8. 5.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 5.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 5.5.1.1.10 AC/DC-Coupled Mode Pin (VCMO)
          11. 5.5.1.1.11 LVDS Output Common-mode Pin (VBG)
        2. 5.5.1.2 Extended Control Mode
          1. 5.5.1.2.1 Serial Interface
    6. 5.6 Register Maps
      1. 5.6.1 Register Definitions
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Analog Inputs
        1. 6.1.1.1 Acquiring the Input
        2. 6.1.1.2 Driving the ADC in DES Mode
        3. 6.1.1.3 FSR and the Reference Voltage
        4. 6.1.1.4 Out-of-Range Indication
        5. 6.1.1.5 Maximum Input Range
        6. 6.1.1.6 AC-Coupled Input Signals
        7. 6.1.1.7 DC-Coupled Input Signals
        8. 6.1.1.8 Single-Ended Input Signals
      2. 6.1.2 Clock Inputs
        1. 6.1.2.1 CLK Coupling
        2. 6.1.2.2 CLK Frequency
        3. 6.1.2.3 CLK Level
        4. 6.1.2.4 CLK Duty Cycle
        5. 6.1.2.5 CLK Jitter
        6. 6.1.2.6 CLK Layout
      3. 6.1.3 LVDS Outputs
        1. 6.1.3.1 Common-mode and Differential Voltage
        2. 6.1.3.2 Output Data Rate
        3. 6.1.3.3 Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1800S in a System
        1. 6.1.4.1 AutoSync Feature
        2. 6.1.4.2 DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. 6.1.5.1 Temperature Sensor
        2. 6.1.5.2 Clocking Device
        3. 6.1.5.3 Amplifiers for Analog Input
        4. 6.1.5.4 Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Specification Definitions
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

2 Revision History

Changes from P Revision (July 2015) to Q Revision

  • Changed cross-reference in last paragraph of Description section to point to correct section Go

Changes from O Revision (January 2014) to P Revision

  • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from N Revision (MARCH 2013) to O Revision

  • Added notification that Aperture Delay Adjust feature cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) for CLK frequencies above 1600 MHz in multiple sections where applicableGo

Changes from M Revision (March 2013) to N Revision

  • Changed layout of National Data Sheet to TI formatGo
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |