The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic latency. The SYSREF signal must be captured by a deterministic device clock (CLK±) edge at each system power-on and at each device in the system. This requirement imposes setup and hold constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all system operating conditions. The ADC12DLx500 includes a number of features to simplify this synchronization process and to relax system timing constraints:

• The ADC12DLx500 uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input frequency by half and double the timing window for SYSREF (see Table 6-3)
• A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid in meeting setup and hold times over all conditions; see the Section 6.3.4.3.1 section
• Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (t_AD adjust) to shift the ADC sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the ADC sampling instance); see the Section 6.3.4.3.2 section