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ZHCSUL6 February 2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500

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ACF|256
- MPBGAO1C

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5.9 Timing Requirements

			MIN	NOM	MAX	UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
f_CLK	Input clock frequency (CLK+, CLK–), both single-channel and dual-channel modes⁽¹⁾		500⁽³⁾		2500	MHz
t_CLK	Input clock period (CLK+, CLK–), both single-channel and dual-channel modes⁽¹⁾		400		2000⁽⁴⁾	ps
SYSREF (SYSREF+, SYSREF–)
t_INV(SYSREF)	Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register⁽²⁾			49		ps
t_INV(TEMP)	Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register			0		ps/°C
t_INV(VA11)	Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register			0.36		ps/mV
t_STEP(SP)	Delay of SYSREF_POS LSB	SYSREF_ZOOM = 0		77		ps
t_STEP(SP)	Delay of SYSREF_POS LSB	SYSREF_ZOOM = 1		24		ps
t_{(PH_SYS)}	Minimum SYSREF± assertion duration after SYSREF± rising edge event			4		ns
t_{(PL_SYS)}	Minimum SYSREF± deassertion duration after SYSREF± falling edge event			4		ns
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
f_CLK(SCLK)	Serial clock frequency		0		15.625	MHz
t_(PH)	Serial clock high value pulse width		32			ns
t_(PL)	Serial clock low value pulse width		32			ns
t_SU(SCS)	Setup time from SCS to rising edge of SCLK		25			ns
t_H(SCS)	Hold time from rising edge of SCLK to SCS		3			ns
t_SU(SDI)	Setup time from SDI to rising edge of SCLK		25			ns
t_H(SDI)	Hold time from rising edge of SCLK to SDI		3			ns

(1) Unless functionally limited to a smaller range than described in the LVDS Output Modes table based on programmed LVDS output mode.

(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for SYSREF capture, see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by t_INV(SYSREF), indicates the portion of the CLK± period (t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that were used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.

(3) Minimum sampling clock down to 0°C. 800MHz below 0°C to -40°C.

(4) Minimum period down to 0°C. 1250ps below 0°C to -40°C.