The PD input pin allows ADC12DL3200 devices to be entirely powered down. Power-down can also be controlled by MODE (see the device configuration register). The LVDS data output drivers are disabled when PD is high. When the device returns to normal operation, the LVDS interface must be re-established, which results in the ADC data pipeline containing meaningless information so the system must wait a sufficient time for the data to be flushed.