The CLK_ALM register bit indicates if the internal clocks may have been upset. The clocks in channel A are continuously compared to channel B. If these clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to function properly, follow this usage model:

1. Program LVDS_EN = 0
2. Ensure the device is configured to use both channels (PD_ACH = 0, PD_BCH = 0)
3. Program LVDS_EN = 1
4. Write CLK_ALM = 1 to clear CLK_ALM
5. Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
6. When exiting global power-down (via MODE in the DEVICE_CONFIG register or via the PD pin), the CLK_ALM status bit can be set and must be cleared by writing a 1 to CLK_ALM