The ADC12DLx500 uses a low-voltage differential signaling (LVDS) interface to output the digital samples. This interface offers simplicity in its implementation compared to serialized interfaces and provides low latency for latency-sensitive applications. The interface uses up to 48 data pairs, four DDR clocks, and four strobe signals arranged in four 12-bit data buses. Strobe signals simplify synchronization across buses and synchronization between multiple devices. The strobe can be generated internally or mirrored from the TMSTP± or SYSREF± inputs. Flexible strobe configurations allow tradeoffs in reliability or number of LVDS pairs and the on-the-fly use of strobe is SPI or pin selectable.

Digital interface scrambling is available to avoid spurious noise generated by the digital interface from leaking into the ADC samples. The receiver must undo the scrambling operation to extract the proper digital samples (see the Section 6.4.5.5 section) when used. Scrambling is optional.