Foreground calibration mode inherently calibrates the offsets of the ADC cores; however, the input buffers sit outside of the calibration loop. Therefore, the offsets are not calibrated by the standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer offsets result in a shift in the mid-code output (DC offset) with no input. Also, in single-channel mode, uncalibrated input buffer offsets can result in a fixed spur at f_S / 2. A separate calibration is provided to correct the input buffer offsets.

There must be no signals at or near DC or aliased signals that fall at or near DC to properly calibration the offsets. Requiring the system to make sure this condition during normal operation or have the ability to mute the input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the calibration one time as part of the foreground calibration procedure.

The offset calibration correction uses the input offset voltage trim registers (see Section 6.4.9) to correct the offset. When offset calibration is used, it must not be written by the user. The calibrated values can be read by reading the OADJ_x_FG0_VINy and OADJ_x_FG90_VINy registers, where x is the ADC core (A or B) and y is the input (INA± or INB±), after calibration is completed. Only read the values when FG_DONE is read as 1 when using foreground offset calibration (CAL_OS = 1).