The ADC12DLx500 contains a delay adjustment on the device clock (sampling clock) input path, called t_AD adjust, that can be used to shift the sampling instance within the device to align sampling instances among multiple devices or for external interleaving of multiple ADC12DLx500 devices. Further, t_AD adjust can be used for automatic SYSREF calibration to simplify synchronization; see the Section 6.3.4.3.2 section. Aperture delay adjustment is implemented in a way that adds no additional noise to the clock path, however a slight degradation in aperture jitter (t_AJ) is possible at large values of TAD_COARSE because of internal clock path attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input frequencies (see t_AJ in the Section 5.11 table). This feature is programmed using TAD_INV, TAD_COARSE, and TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting in a delay equal to half the clock period. Table 6-4 summarizes the step sizes and ranges of the TAD_COARSE and TAD_FINE variable analog delays. All three delay options are independent and can be used in conjunction. All clocks within the device are shifted by the programmed t_AD adjust amount, which results in a shift of the timing of the LVDS data interface and affects the capture of SYSREF.

To maintain timing alignment between converters, stable and matched power-supply voltages and device temperatures must be provided.

Aperture delay adjustment can be changed on-the-fly during normal operation, however changing the aperture delay also shifts the clock for the LVDS data interface (DxCLK±, DxSTR±, and Dx[11:0]±). The receiving circuit must be tolerant of shifts in the LVDS data timing. Use of the TAD_RAMP feature may help the receiver avoid loss of synchronization; see the Section 6.3.4.2 section.