ZHCSUL6 February   2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics - ADC12DL500
    13. 5.13 Typical Characteristics - ADC12DL1500 (1GSPS)
    14. 5.14 Typical Characteristics - ADC12DL1500 (1.5GSPS)
    15. 5.15 Typical Characteristics - ADC12DL2500 (2GSPS)
    16. 5.16 Typical Characteristics - ADC12DL2500 (2.5GSPS)
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
        5. 6.3.2.5 Internal Dither
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 LVDS Digital Interface
        1. 6.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 6.3.5.1.1 Dedicated Strobe Pins
          2. 6.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 6.3.5.1.3 LSB Replacement With a Strobe
          4. 6.3.5.1.4 Strobe Over All Data Pairs
      6. 6.3.6 Alarm Monitoring
        1. 6.3.6.1 Clock Upset Detection
      7. 6.3.7 Temperature Monitoring Diode
      8. 6.3.8 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 6.4.2 Internal Dither Modes
      3. 6.4.3 Single-Channel Mode (DES Mode)
      4. 6.4.4 LVDS Output Driver Modes
      5. 6.4.5 LVDS Output Modes
        1. 6.4.5.1 Staggered Output Mode
        2. 6.4.5.2 Aligned Output Mode
        3. 6.4.5.3 Reducing the Number of Strobes
        4. 6.4.5.4 Reducing the Number of Data Clocks
        5. 6.4.5.5 Scrambling
        6. 6.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 6.4.5.6.1 Active Pattern
          2. 6.4.5.6.2 Synchronization Pattern
          3. 6.4.5.6.3 User-Defined Test Pattern
      6. 6.4.6 Power-Down Modes
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 80
        6. 6.5.1.6 Streaming Mode
        7. 6.5.1.7 82
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Reconfigurable Dual-Channel 2.5GSPS or Single-Channel 5GSPS Oscilloscope
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
          3. 7.2.1.1.3 ADC12DLx500
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Register Maps
    1. 8.1 SPI_REGISTER_MAP Registers
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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5.5 Electrical Characteristics: DC Specifications

Typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), foreground calibration; minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
Resolution Resolution with no missing codes 12 Bits
ADC12DL500
DNL Differential nonlinearity Maximum positive excursion from ideal step size 0.17 LSB
Maximum negative excursion from ideal step size -0.14
INL Integral nonlinearity Maximum positive excursion from ideal transfer function 1 LSB
Maximum negative excursion from ideal transfer function -1.5
ADC12DL1500
DNL Differential nonlinearity Maximum positive excursion from ideal step size 0.14 LSB
Maximum negative excursion from ideal step size -0.14
INL Integral nonlinearity Maximum positive excursion from ideal transfer function 1 LSB
Maximum negative excursion from ideal transfer function -1
ADC12DL2500
DNL Differential nonlinearity Maximum positive excursion from ideal step size 0.17 LSB
Maximum negative excursion from ideal step size -0.19
INL Integral nonlinearity Maximum positive excursion from ideal transfer function 2.3 LSB
Maximum negative excursion from ideal transfer function -1
ANALOG INPUTS (INA±, INB±)
VOFF Offset Error CAL_OS = 0 ±2.0 mV
CAL_OS = 1 ±0.3 mV
VOFF_ADJ Input offset voltage adjustment range Available offset correction range (see CAL_OS bit in the CAL_CFGO register or the OADJ_A_FG0_VINA register)   ±55   mV
VOFF_ DRIFT Offset drift Foreground calibration at nominal temperature only 14 µV/°C
Foreground calibration at each temperature 4
VIN_FSR Analog differential input full-scale range Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) 800 mVPP
Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) 1040
Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) 480
VIN_FSR_DRIFT Analog differential input full-scale range drift Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift 0.037 %/°C
Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift 0.006
VIN_FSR_MATCH Analog differential input full-scale range matching Matching between INA± and INB±, default setting, dual channel mode 0.53 %
RIN Single-ended input resistance to AGND Each input terminal is terminated to AGND, measured at TA = 25°C 50 Ω
RIN_ TEMPCO Input termination linear temperature coefficient 11.6 mΩ/°C
CIN Single-ended input capacitance Single-channel mode measured at DC 0.45 pF
Dual-channel mode measured at DC 0.45
TEMPERATURE DIODE CHARACTERISTICS (TDIODE±)
ΔVBE Temperature diode voltage slope Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Perform offset measurements with the device unpowered or with the PD pin asserted to minimize device self-heating. -1.5 mV/°C
BANDGAP VOLTAGE OUTPUT (BG)
VBG Reference output voltage IL ≤ 100 µA 1.1 V
VBG_ DRIFT Reference output temperature drift IL ≤ 100 µA -125 µV/°C
CLOCK INPUTS (CLK±, SYSREF±, TMSTP±)
ZT Internal termination Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 100 Ω
Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 50
VCM Input common-mode voltage, self-biased Self-biasing common-mode voltage for CLK± when AC coupled (DEVCLK_LVPECL_EN must be set to 0) 0.3 V
Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1). 0.3
Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0). VA11
CL_DIFF Differential input capacitance Between positive and negative differential input pins 0.1 pF
CL_SE Single-ended input capacitance Each input to ground 0.5 pF
LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±)
VDIFF Differential output peak-to-peak voltage, DC measurement Default swing (HSM), 100-Ω load 720 mVPP-DIFF
Low swing (LSM), 100-Ω load 350
Low swing high-Z mode (HZM), high-impedance load 380
VCM Output common-mode voltage, tracks with VLVDS VLVDS = 1.9 V 1.3 V
VLVDS = 1.1 V 0.5
IOS_DIFF Differential short-circuit current Positive and negative outputs shorted together 5 mA
IOS_GND Short-circuit current to ground Either positive or negative output tied to ground 20 mA
ZDIFF Differential output impedance Measured at DC 300 Ω
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE
IIH High-level input current 40 µA
IIL Low-level input current –40 µA
CI Input capacitance 2 pF
VOH High-level output voltage ILOAD = –400 µA 1.65 V
VOL Low-level output voltage ILOAD = 400 µA 150 mV
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