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ZHCSPX2B June 2022 – October 2024 ADC12QJ1600-EP

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7.2.1.2.2 Calculating Clock and SerDes Frequencies

The example LiDAR system uses four ADC channels running at 1 GSPS and the on-chip clock features of the device to reduce the system size and cost. The device is clocked by a 50-MHz crystal through the single-ended clock input (CLK_SE) and the integrated clock features are used to eliminate external clocking components. The internal PLL (C-PLL) generates the 1 GHz sampling clock for the ADC cores. The 50 MHz PLL reference is repeated through the PLLREFO output to the FPGA to generate the FPGA internal clocks including the application layer clock. The 50 MHz reference is divided down in the FPGA to generate the SYSREF signal which is sent to both the FPGA JESD204C core and to the device to achieve deterministic latency.

There are a number of clocking frequencies used in the example system shown in Figure 7-1. The reference clock frequency (f_REF) is chosen by the designer and in this case is chosen as 50 MHz, which is the minimum supported reference frequency and which multiplies easily to 1 GHz. The sampling rate is set by the system requirements which is 1 GSPS (f_S). The V, P and N dividers of the C-PLL are chosen as described in the Converter PLL (C-PLL) for Sampling Clock Generation section which, along with the reference frequency, determines the VCO frequency (f_VCO). JMODE 8 was chosen to stay within the FPGA SerDes requirements (4 lanes, 12.5 Gbps max rate) which is a 64B or 66B mode. TRIGOUT provides the FPGA SerDes PLL reference clock to the FPGA (f_TRIGOUT) and PLLREFO provides the reference clock for the FPGA core logic. ORC (f_ORC) and ORD (f_ORD) provide additional clock outputs, if needed, for the FPGA or peripheral devices. SYSREF is generated within the FPGA and sent to the ADC in order to achieve deterministic latency. This is not usually recommended due to timing constraints, however the low reference frequency (50 MHz) significantly relaxes the SYSREF setup and hold timing and the SYSREF Windowing feature allows verification of proper capture timing of SYSREF relative to the reference clock. The SYSREF frequency must divide evenly into the reference clock frequency, in addition to meeting the JESD204 protocol requirements, in order to achieve deterministic latency due to the use of the C-PLL. The frequency and rate calculations are summarized in Table 7-2.

Table 7-2 Clock and SerDes Frequency Calculations for Example LiDAR Digitizer

Clock	Symbol	Calculation	Frequency
Reference Clock	f_REF	Chosen by designer	50 MHz
Sampling Rate	f_S	System requirement	1 GSPS
C-PLL VCO	f_VCO	f_VCO = f_Sx P x V where P is 2 and V is 4	8 GHz
SerDes Linerate	f_LINERATE	f_LINERATE = f_Sx R where R is 12.375 for JMODE 8 (see Table 6-15)	12.375 Gbps / Lane (4 lanes)
TRIGOUT Clock Output	f_TRIGOUT	f_TRIGOUT = f_LINERATE/ RX_DIV where RX_DIV is 32 (TRIGOUT_CTRL=0x81)	386.71875 MHz
SYSREF	f_SYSREF	f_SYSREF = f_LINERATE/ (66 x 32 x E x n) where E is 3 for JMODE 8 (64B/66B mode) and n is chosen such that f_SYSREF is an integer division of f_REF (n = 5)	390.625 kHz
ORC Clock Output	f_ORC	f_ORC = f_REF/2 (See Table 6-4)	25 MHz
ORD Clock Output	f_ORD	f_ORD = f_REF (See Table 6-5)	50 MHz
FPGA Core Clock	f_FPGA	f_FPGA = f_REF x M ⁽¹⁾⁽²⁾ where M is an integer value, chosen as 5	250 MHz (4 samples per cycle)

(1) In the clock configuration shown, the FPGA clock which runs the JESD204C core must be an integer multiplication of f_REF in order to properly pass SYSREF from the reference clock domain to the core clock domain to achieve deterministic latency. In many cases the JESD204C IP may expect a clock rate of f_LINERATE/66, which results in 187.5 MHz for the example. Some JESD204C IP cores may not allow the JESD204C clock frequency to deviate from this requirement and therefore IP provider should be consulted. If the requirement described for the FPGA core clock cannot be met than deterministic latency cannot be achieved (operation without deterministic latency is still supported).

(2) If the application layer runs at a different clock rate than the JESD204C core, then some logic may be needed to pass data between clock domains while maintain timing information. Further, many JESD204C IP cores output 64 bits per clock cycle which may include fractions of a sample (such as in JMODE 8) and therefore gearbox logic may be needed to transition to the desired sample rate.