ZHCSPP4A june   2022  – july 2023 ADC12QJ1600-SP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Revision History
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Switching Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Protection
        2. 8.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.1.3 Analog Input Offset Adjust
        4. 8.3.1.4 ADC Core
          1. 8.3.1.4.1 ADC Theory of Operation
          2. 8.3.1.4.2 ADC Core Calibration
          3. 8.3.1.4.3 Analog Reference Voltage
          4. 8.3.1.4.4 ADC Over-range Detection
          5. 8.3.1.4.5 Code Error Rate (CER)
      2. 8.3.2 Temperature Monitoring Diode
      3. 8.3.3 Timestamp
      4. 8.3.4 Clocking
        1. 8.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 8.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 8.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 8.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 8.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 8.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 8.3.5 JESD204C Interface
        1. 8.3.5.1  Transport Layer
        2. 8.3.5.2  Scrambler
        3. 8.3.5.3  Link Layer
        4. 8.3.5.4  8B or 10B Link Layer
          1. 8.3.5.4.1 Data Encoding (8B or 10B)
          2. 8.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 8.3.5.4.3 Code Group Synchronization (CGS)
          4. 8.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 8.3.5.4.5 Frame and Multiframe Monitoring
        5. 8.3.5.5  64B or 66B Link Layer
          1. 8.3.5.5.1 64B or 66B Encoding
          2. 8.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 8.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 8.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 8.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 8.3.5.5.3 Initial Lane Alignment
          4. 8.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 8.3.5.6  Physical Layer
          1. 8.3.5.6.1 SerDes Pre-Emphasis
        7. 8.3.5.7  JESD204C Enable
        8. 8.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 8.3.5.9  Operation in Subclass 0 Systems
        10. 8.3.5.10 Alarm Monitoring
          1. 8.3.5.10.1 Clock Upset Detection
          2. 8.3.5.10.2 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. 8.4.2.1 JESD204C Transport Layer Data Formats
        2. 8.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 8.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1. 8.4.4.1 Serializer Test-Mode Details
        2. 8.4.4.2 PRBS Test Modes
        3. 8.4.4.3 Clock Pattern Mode
        4. 8.4.4.4 Ramp Test Mode
        5. 8.4.4.5 Short and Long Transport Test Mode
          1. 8.4.4.5.1 Short Transport Test Pattern
        6. 8.4.4.6 D21.5 Test Mode
        7. 8.4.4.7 K28.5 Test Mode
        8. 8.4.4.8 Repeated ILA Test Mode
        9. 8.4.4.9 Modified RPAT Test Mode
      5. 8.4.5 Calibration Modes and Trimming
        1. 8.4.5.1 Foreground Calibration Mode
        2. 8.4.5.2 Background Calibration Mode
        3. 8.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 8.4.6 Offset Calibration
      7. 8.4.7 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
      7. 8.5.7 SPI_Register_Map Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Analog Front-End Requirements
          2. 9.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 9.2.1.3 Application Curves
    3. 9.3 Initialization Set Up
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Sequencing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALR|144
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.4.4.1 Serializer Test-Mode Details

Test modes are enabled by setting JTEST to the desired test mode. Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer outputs (number of lanes, rate) are powered up based on JMODE. Only enable the test modes when the JESD204C link is disabled. Figure 8-12 provides a diagram showing the various test mode insertion points.

GUID-34A7717D-F91B-400C-AC3C-7E5DCC703D6B-low.gifFigure 8-12 Test Mode Insertion Points
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |